+2011-04-11 Julian Brown <julian@codesourcery.com>
+
+ * config/tc-arm.c (parse_psr): Add LHS argument. Improve support
+ for *APSR bitmasks.
+ (operand_parse_code): Replace OP_PSR with OP_wPSR and OP_rPSR.
+ Remove OP_RVC_PSR.
+ (parse_operands): Likewise.
+ (do_mrs): Tweak error message for constraint.
+ (do_t_mrs): Update constraints for changes to APSR support.
+ (do_t_msr): Likewise. Don't set PSR_f flag here.
+ (psrs): Remove "g", "nzcvq", "nzcvqg".
+ (insns): Tweak entries for msr and mrs instructions.
+
2011-04-11 Kai Tietz <ktietz@redhat.com>
* config/tc-i386.c (x86_cons): Initialize adjust with zero.
/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
or a bitmask suitable to be or-ed into the ARM msr instruction. */
static int
-parse_psr (char **str)
+parse_psr (char **str, bfd_boolean lhs)
{
char *p;
unsigned long psr_field;
const struct asm_psr *psr;
char *start;
+ bfd_boolean is_apsr = FALSE;
+ bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
p = *str;
if (strncasecmp (p, "SPSR", 4) == 0)
- psr_field = SPSR_BIT;
- else if (strncasecmp (p, "CPSR", 4) == 0
- || (strncasecmp (p, "APSR", 4) == 0
- && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m)))
- psr_field = 0;
- else
+ {
+ if (m_profile)
+ goto unsupported_psr;
+
+ psr_field = SPSR_BIT;
+ }
+ else if (strncasecmp (p, "CPSR", 4) == 0)
+ {
+ if (m_profile)
+ goto unsupported_psr;
+
+ psr_field = 0;
+ }
+ else if (strncasecmp (p, "APSR", 4) == 0)
+ {
+ /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
+ and ARMv7-R architecture CPUs. */
+ is_apsr = TRUE;
+ psr_field = 0;
+ }
+ else if (m_profile)
{
start = p;
do
p++;
while (ISALNUM (*p) || *p == '_');
+ if (strncasecmp (start, "iapsr", 5) == 0
+ || strncasecmp (start, "eapsr", 5) == 0
+ || strncasecmp (start, "xpsr", 4) == 0
+ || strncasecmp (start, "psr", 3) == 0)
+ p = start + strcspn (start, "rR") + 1;
+
psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
p - start);
+
if (!psr)
return FAIL;
+ /* If APSR is being written, a bitfield may be specified. Note that
+ APSR itself is handled above. */
+ if (psr->field <= 3)
+ {
+ psr_field = psr->field;
+ is_apsr = TRUE;
+ goto check_suffix;
+ }
+
*str = p;
- return psr->field;
+ /* M-profile MSR instructions have the mask field set to "10", except
+ *PSR variants which modify APSR, which may use a different mask (and
+ have been handled already). Do that by setting the PSR_f field
+ here. */
+ return psr->field | (lhs ? PSR_f : 0);
}
+ else
+ goto unsupported_psr;
p += 4;
+check_suffix:
if (*p == '_')
{
/* A suffix follows. */
p++;
while (ISALNUM (*p) || *p == '_');
- psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
- p - start);
- if (!psr)
- goto error;
+ if (is_apsr)
+ {
+ /* APSR uses a notation for bits, rather than fields. */
+ unsigned int nzcvq_bits = 0;
+ unsigned int g_bit = 0;
+ char *bit;
+
+ for (bit = start; bit != p; bit++)
+ {
+ switch (TOLOWER (*bit))
+ {
+ case 'n':
+ nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
+ break;
+
+ case 'z':
+ nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
+ break;
+
+ case 'c':
+ nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
+ break;
+
+ case 'v':
+ nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
+ break;
+
+ case 'q':
+ nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
+ break;
+
+ case 'g':
+ g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
+ break;
+
+ default:
+ inst.error = _("unexpected bit specified after APSR");
+ return FAIL;
+ }
+ }
+
+ if (nzcvq_bits == 0x1f)
+ psr_field |= PSR_f;
+
+ if (g_bit == 0x1)
+ {
+ if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
+ {
+ inst.error = _("selected processor does not "
+ "support DSP extension");
+ return FAIL;
+ }
+
+ psr_field |= PSR_s;
+ }
+
+ if ((nzcvq_bits & 0x20) != 0
+ || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
+ || (g_bit & 0x2) != 0)
+ {
+ inst.error = _("bad bitmask specified after APSR");
+ return FAIL;
+ }
+ }
+ else
+ {
+ psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
+ p - start);
+ if (!psr)
+ goto error;
- psr_field |= psr->field;
+ psr_field |= psr->field;
+ }
}
else
{
if (ISALNUM (*p))
goto error; /* Garbage after "[CS]PSR". */
- psr_field |= (PSR_c | PSR_f);
+ /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
+ is deprecated, but allow it anyway. */
+ if (is_apsr && lhs)
+ {
+ psr_field |= PSR_f;
+ as_tsktsk (_("writing to APSR without specifying a bitmask is "
+ "deprecated"));
+ }
+ else if (!m_profile)
+ /* These bits are never right for M-profile devices: don't set them
+ (only code paths which read/write APSR reach here). */
+ psr_field |= (PSR_c | PSR_f);
}
*str = p;
return psr_field;
+ unsupported_psr:
+ inst.error = _("selected processor does not support requested special "
+ "purpose register");
+ return FAIL;
+
error:
inst.error = _("flag for {c}psr instruction expected");
return FAIL;
OP_CPSF, /* CPS flags */
OP_ENDI, /* Endianness specifier */
- OP_PSR, /* CPSR/SPSR mask for msr */
+ OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
+ OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
OP_COND, /* conditional code */
OP_TB, /* Table branch. */
- OP_RVC_PSR, /* CPSR/SPSR mask for msr, or VFP control register. */
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
OP_RRnpc_I0, /* ARM register or literal 0 */
case OP_CPSF: val = parse_cps_flags (&str); break;
case OP_ENDI: val = parse_endian_specifier (&str); break;
case OP_oROR: val = parse_ror (&str); break;
- case OP_PSR: val = parse_psr (&str); break;
case OP_COND: val = parse_cond (&str); break;
case OP_oBARRIER_I15:
po_barrier_or_imm (str); break;
goto failure;
break;
- case OP_RVC_PSR:
- po_reg_or_goto (REG_TYPE_VFC, try_banked_reg);
- inst.operands[i].isvec = 1; /* Mark VFP control reg as vector. */
- break;
- try_banked_reg:
+ case OP_wPSR:
+ case OP_rPSR:
po_reg_or_goto (REG_TYPE_RNB, try_psr);
if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
{
goto failure;
}
break;
- try_psr:
- val = parse_psr (&str);
- break;
+ try_psr:
+ val = parse_psr (&str, op_parse_code == OP_wPSR);
+ break;
case OP_APSR_RR:
po_reg_or_goto (REG_TYPE_RN, try_apsr);
case OP_CPSF:
case OP_ENDI:
case OP_oROR:
- case OP_PSR:
- case OP_RVC_PSR:
+ case OP_wPSR:
+ case OP_rPSR:
case OP_COND:
case OP_oBARRIER_I15:
case OP_REGLST:
/* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
!= (PSR_c|PSR_f),
- _("'CPSR' or 'SPSR' expected"));
+ _("'APSR', 'CPSR' or 'SPSR' expected"));
br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
}
{
int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
- if (flags == 0)
- {
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
- _("selected processor does not support "
- "requested special purpose register"));
- }
+ if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
+ constraint (flags != 0, _("selected processor does not support "
+ "requested special purpose register"));
else
- {
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
- _("selected processor does not support "
- "requested special purpose register"));
- /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
- constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
- _("'CPSR' or 'SPSR' expected"));
- }
+ /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
+ devices). */
+ constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
+ _("'APSR', 'CPSR' or 'SPSR' expected"));
inst.instruction |= (flags & SPSR_BIT) >> 2;
inst.instruction |= inst.operands[1].imm & 0xff;
else
flags = inst.operands[0].imm;
- if (flags & ~0xff)
+ if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
{
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1),
- _("selected processor does not support "
- "requested special purpose register"));
+ int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
+
+ constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
+ && (bits & ~(PSR_s | PSR_f)) != 0)
+ || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
+ && bits != PSR_f),
+ _("selected processor does not support requested special "
+ "purpose register"));
}
else
- {
- constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
- _("selected processor does not support "
- "requested special purpose register"));
- flags |= PSR_f;
- }
+ constraint ((flags & 0xff) != 0, _("selected processor does not support "
+ "requested special purpose register"));
Rn = inst.operands[1].reg;
reject_bad_reg (Rn);
{"c", PSR_c},
{"x", PSR_x},
{"s", PSR_s},
- {"g", PSR_s},
/* Combinations of flags. */
{"fs", PSR_f | PSR_s},
{"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
{"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
{"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
-
- /* APSR flags */
- {"nzcvq", PSR_f},
- {"nzcvqg", PSR_s | PSR_f}
};
/* Table of V7M psr names. */
#undef THUMB_VARIANT
#define THUMB_VARIANT & arm_ext_msr
- TCE("mrs", 1000000, f3e08000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
- TCE("msr", 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
+ TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
+ TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
+2011-04-11 Julian Brown <julian@codesourcery.com>
+
+ * gas/arm/mrs-msr-thumb-v7-m.s: New.
+ * gas/arm/mrs-msr-thumb-v7-m.d: New.
+ * gas/arm/mrs-msr-thumb-v7-m-bad.d: New.
+ * gas/arm/mrs-msr-thumb-v7-m-bad.l: New.
+ * gas/arm/mrs-msr-thumb-v7-m-bad.s: New.
+ * gas/arm/mrs-msr-thumb-v7e-m.d: New.
+ * gas/arm/mrs-msr-thumb-v7e-m.s: New.
+ * gas/arm/mrs-msr-arm-v7-a-bad.d: New.
+ * gas/arm/mrs-msr-arm-v7-a-bad.l: New.
+ * gas/arm/mrs-msr-arm-v7-a-bad.s: New.
+ * gas/arm/mrs-msr-arm-v7-a.d: New.
+ * gas/arm/mrs-msr-arm-v7-a.s: New.
+ * gas/arm/mrs-msr-arm-v6.d: New.
+ * gas/arm/mrs-msr-arm-v6.s: New.
+ * gas/arm/mrs-msr-thumb-v6t2.d: New.
+ * gas/arm/mrs-msr-thumb-v6t2.s: New.
+ * gas/arm/arch7.d: Fix typo in disassembly for BASEPRI_MAX,
+ bitmasks for IAPSR etc.
+ * gas/arm/arch7.s: Specify bitmask for APSR writes.
+ * gas/arm/archv6m.s: Likewise.
+ * msr-imm-bad.l: Tweak expected disassembly in error message.
+ * msr-reg-bad.l: Likewise.
+ * msr-imm.d: Tweak expected disassembly.
+ * msr-reg.d: Likewise.
+ * msr-reg-thumb.d: Likewise.
+ * msr-imm.s: Specify bitmask on APSR writes.
+ * msr-reg.s: Add comment about deprecated usage.
+
2011-04-11 Dan McDonald <dan@wellkeeper.com>
PR gas/12296
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
-0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
+0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
-0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR), r0
-0+0dc <[^>]*> f380 8801 msr IAPSR, r0
-0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
-0+0e4 <[^>]*> f380 8803 msr PSR, r0
+0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
+0+0dc <[^>]*> f380 8801 msr IAPSR_nzcvq, r0
+0+0e0 <[^>]*> f380 8802 msr EAPSR_nzcvq, r0
+0+0e4 <[^>]*> f380 8803 msr PSR_nzcvq, r0
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
0+0ec <[^>]*> f380 8806 msr EPSR, r0
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
-0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
+0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
-0+114 <[^>]*> f380 8803 msr PSR, r0
+0+114 <[^>]*> f380 8803 msr PSR_nzcvq, r0
0+118 <[^>]*> df00 svc 0
mrs r0, basepri_max
mrs r0, faultmask
mrs r0, control
- msr apsr, r0
- msr iapsr, r0
- msr eapsr, r0
- msr psr, r0
+ msr apsr_nzcvq, r0
+ msr iapsr_nzcvq, r0
+ msr eapsr_nzcvq, r0
+ msr psr_nzcvq, r0
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
msr faultmask, r0
msr control, r0
mrs r0, xpsr
- msr xpsr, r0
+ msr xpsr_nzcvq, r0
svc 0
.align 2
.global foo
foo:
- msr apsr,r6
+ msr apsr_nzcvq,r6
msr epsr,r9
mrs r2, iapsr
yield
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MRS/MSR test, architecture v6, ARM mode
+
+.*: file format .*
+
+
+Disassembly of section .text:
+0+00 <[^>]*> e10f4000 mrs r4, CPSR
+0+04 <[^>]*> e10f5000 mrs r5, CPSR
+0+08 <[^>]*> e14f6000 mrs r6, SPSR
+0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
+0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
+0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+0+18 <[^>]*> e128f004 msr CPSR_f, r4
+0+1c <[^>]*> e128f005 msr CPSR_f, r5
+0+20 <[^>]*> e169f006 msr SPSR_fc, r6
--- /dev/null
+ .arch armv6
+ .text
+ .arm
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvq, #0x40000000
+ msr cpsr_f, #0x20000000
+ msr spsr, #0x10000000
+ msr apsr_nzcvq, r4
+ msr cpsr_f, r5
+ msr spsr, r6
--- /dev/null
+# name: MRS/MSR negative test, architecture v7-A, ARM mode
+# error-output: mrs-msr-arm-v7-a-bad.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r4,apsr_nzcvq'
+[^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,iapsr'
+[^:]*:7: Error: selected processor does not support requested special purpose register -- `msr iapsr,r4'
+[^:]*:8: writing to APSR without specifying a bitmask is deprecated
--- /dev/null
+ .arch armv7-a
+ .text
+ .arm
+
+ mrs r4, apsr_nzcvq
+ mrs r5, iapsr
+ msr iapsr, r4
+ msr apsr, r5
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MRS/MSR test, architecture v7-A, ARM mode
+
+.*: file format .*
+
+
+Disassembly of section .text:
+0+00 <[^>]*> e10f4000 mrs r4, CPSR
+0+04 <[^>]*> e10f5000 mrs r5, CPSR
+0+08 <[^>]*> e14f6000 mrs r6, SPSR
+0+0c <[^>]*> e32cf101 msr CPSR_fs, #1073741824 ; 0x40000000
+0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
+0+14 <[^>]*> e369f201 msr SPSR_fc, #268435456 ; 0x10000000
+0+18 <[^>]*> e128f004 msr CPSR_f, r4
+0+1c <[^>]*> e128f005 msr CPSR_f, r5
+0+20 <[^>]*> e169f006 msr SPSR_fc, r6
--- /dev/null
+ .arch armv7-a
+ .text
+ .arm
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvqg, #0x40000000
+ msr cpsr_f, #0x20000000
+ msr spsr, #0x10000000
+ msr apsr_nzcvq, r4
+ msr cpsr_f, r5
+ msr spsr, r6
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MRS/MSR test, architecture v6t2, Thumb mode
+
+.*: file format .*
+
+
+Disassembly of section .text:
+0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+0+04 <[^>]*> f3ef 8500 mrs r5, CPSR
+0+08 <[^>]*> f3ff 8600 mrs r6, SPSR
+0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
+0+10 <[^>]*> f385 8800 msr CPSR_f, r5
+0+14 <[^>]*> f396 8900 msr SPSR_fc, r6
--- /dev/null
+ .arch armv6t2
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, cpsr
+ mrs r6, spsr
+ msr apsr_nzcvqg, r4
+ msr cpsr_f, r5
+ msr spsr, r6
--- /dev/null
+# name: MRS/MSR negative test, architecture v7-M, Thumb mode
+# error-output: mrs-msr-thumb-v7-m-bad.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:5: Error: selected processor does not support requested special purpose register -- `mrs r4,cpsr'
+[^:]*:6: Error: selected processor does not support requested special purpose register -- `mrs r5,spsr'
+[^:]*:7: Error: selected processor does not support DSP extension -- `msr apsr_nzcvqg,r4'
+[^:]*:8: Error: selected processor does not support DSP extension -- `msr iapsr_nzcvqg,r5'
+[^:]*:9: Error: bad bitmask specified after APSR -- `msr xpsr_nncvq,r6'
+[^:]*:10: Error: bad bitmask specified after APSR -- `msr xpsr_nzcv,r7'
+[^:]*:11: Error: selected processor does not support requested special purpose register -- `msr cpsr_f,r7'
+[^:]*:12: Error: selected processor does not support requested special purpose register -- `msr spsr,r8'
+[^:]*:13: Error: syntax error -- `msr primask_nzcvq,r9'
--- /dev/null
+ .arch armv7-m
+ .text
+ .thumb
+
+ mrs r4, cpsr
+ mrs r5, spsr
+ msr apsr_nzcvqg, r4
+ msr iapsr_nzcvqg, r5
+ msr xpsr_nncvq, r6
+ msr xpsr_nzcv, r7
+ msr cpsr_f, r7
+ msr spsr, r8
+ msr primask_nzcvq, r9
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MRS/MSR test, architecture v7-M, Thumb mode
+
+
+.*: file format .*
+
+
+Disassembly of section .text:
+0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
+0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
+0+0c <[^>]*> f383 8803 msr PSR_nzcvq, r3
+0+10 <[^>]*> f384 8800 msr CPSR_f, r4
+0+14 <[^>]*> f385 8801 msr IAPSR_nzcvq, r5
+0+18 <[^>]*> f386 8810 msr PRIMASK, r6
--- /dev/null
+ .arch armv7-m
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, eapsr
+ mrs r6, primask
+ msr xpsr_nzcvq, r3
+ msr apsr_nzcvq, r4
+ msr iapsr_nzcvq, r5
+ msr primask, r6
--- /dev/null
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MRS/MSR test, architecture v7e-M, Thumb mode
+
+.*: file format .*
+
+
+Disassembly of section .text:
+0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
+0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
+0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
+0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
+0+10 <[^>]*> f385 8401 msr IAPSR_g, r5
+0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
--- /dev/null
+ .arch armv7e-m
+ .text
+ .thumb
+
+ mrs r4, apsr
+ mrs r5, eapsr
+ mrs r6, primask
+ msr apsr_nzcvqg, r4
+ msr iapsr_g, r5
+ msr basepri_max, r6
[^:]*: Assembler messages:
-[^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR,#0xc0000004'
+[^:]*:9: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:10: Error: Thumb encoding does not support an immediate here -- `msr APSR_g,#0xc0000004'
[^:]*:11: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvq,#0xc0000004'
[^:]*:12: Error: Thumb encoding does not support an immediate here -- `msr APSR_nzcvqg,#0xc0000004'
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <[^>]*> e329f113 msr CPSR_fc, #-1073741820 ; 0xc0000004
+00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
00000004 <[^>]*> e324f113 msr CPSR_s, #-1073741820 ; 0xc0000004
00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
0000000c <[^>]*> e32cf113 msr CPSR_fs, #-1073741820 ; 0xc0000004
@ Write to Special Register from Immediate
@ Write to application status register
- msr APSR,#0xc0000004
+ msr APSR_nzcvq,#0xc0000004
msr APSR_g,#0xc0000004
msr APSR_nzcvq,#0xc0000004
msr APSR_nzcvqg,#0xc0000004
[^:]*: Assembler messages:
-[^:]*:9: Error: syntax error -- `msr APSR_g,r9'
-[^:]*:10: Error: syntax error -- `msr APSR_nzcvq,r9'
-[^:]*:11: Error: syntax error -- `msr APSR_nzcvqg,r9'
+[^:]*:8: writing to APSR without specifying a bitmask is deprecated
+[^:]*:9: Error: selected processor does not support DSP extension -- `msr APSR_g,r9'
+[^:]*:11: Error: selected processor does not support DSP extension -- `msr APSR_nzcvqg,r9'
[^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
[^:]*:15: Error: selected processor does not support requested special purpose register -- `msr CPSR_s,r9'
[^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
# as: -march=armv7-a -mthumb
# source: msr-reg.s
# objdump: -dr --prefix-addresses --show-raw-insn
+# warning: writing to APSR without specifying a bitmask is deprecated
# skip: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <[^>]*> f389 8900 msr CPSR_fc, r9
+00000000 <[^>]*> f389 8800 msr CPSR_f, r9
00000004 <[^>]*> f389 8400 msr CPSR_s, r9
00000008 <[^>]*> f389 8800 msr CPSR_f, r9
0000000c <[^>]*> f389 8c00 msr CPSR_fs, r9
# name: MSR register operands
# as: -march=armv7-a
# objdump: -dr --prefix-addresses --show-raw-insn
+# warning: writing to APSR without specifying a bitmask is deprecated
.*: +file format .*arm.*
Disassembly of section .text:
-00000000 <[^>]*> e129f009 msr CPSR_fc, r9
+00000000 <[^>]*> e128f009 msr CPSR_f, r9
00000004 <[^>]*> e124f009 msr CPSR_s, r9
00000008 <[^>]*> e128f009 msr CPSR_f, r9
0000000c <[^>]*> e12cf009 msr CPSR_fs, r9
.syntax unified
@ Write to Special Register from register
- msr APSR,r9
+ msr APSR,r9 @ deprecated usage.
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
+2011-04-11 Julian Brown <julian@codesourcery.com>
+
+ * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
+ (print_insn_thumb32): Add APSR bitmask support.
+
2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
* arm-dis.c (print_insn): init vars moved into private_data structure.
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
- case 18: return "BASEPRI_MASK";
+ case 18: return "BASEPRI_MAX";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
else
func (stream, "(UNDEF: %lu)", sysm);
}
+ else if ((given & 0xff) <= 3)
+ {
+ func (stream, "%s_", psr_name (given & 0xff));
+
+ if (given & 0x800)
+ func (stream, "nzcvq");
+ if (given & 0x400)
+ func (stream, "g");
+ }
else
{
func (stream, psr_name (given & 0xff));
projects / binutils-gdb.git / commitdiff