projects / gem5.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 931ec6b)
ruby: set the is_icache param for caches
authorMalek Musleh <malek.musleh@gmail.com>
Sat, 27 Oct 2012 21:04:30 +0000 (16:04 -0500)
committerMalek Musleh <malek.musleh@gmail.com>
Sat, 27 Oct 2012 21:04:30 +0000 (16:04 -0500)
This patch sets the is_icache param for the L1 caches used in
the MESI and the MOESI CMP directory protocols.

configs/ruby/MESI_CMP_directory.py patch | blob | history
configs/ruby/MOESI_CMP_directory.py patch | blob | history

diff --git a/configs/ruby/MESI_CMP_directory.py b/configs/ruby/MESI_CMP_directory.py
index 35f8575342c6f732f574aed746663477bad1f432..6694223cfe8bc4e8fd435fc14ab71fd7a7713645 100644 (file)
--- a/configs/ruby/MESI_CMP_directory.py
+++ b/configs/ruby/MESI_CMP_directory.py
@@ -80,10 +80,12 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
         #
         l1i_cache = L1Cache(size = options.l1i_size,
                             assoc = options.l1i_assoc,
-                            start_index_bit = block_size_bits)
+                            start_index_bit = block_size_bits,
+                            is_icache = True)
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc,
-                            start_index_bit = block_size_bits)
+                            start_index_bit = block_size_bits,
+                            is_icache = False)
 
         l1_cntrl = L1Cache_Controller(version = i,
                                       cntrl_id = cntrl_count,
diff --git a/configs/ruby/MOESI_CMP_directory.py b/configs/ruby/MOESI_CMP_directory.py
index dbe81497782f5b9fffd9df7b693e7320343b47e7..3a69b657e7d6aac8fc2953559c29322dc9bc11cb 100644 (file)
--- a/configs/ruby/MOESI_CMP_directory.py
+++ b/configs/ruby/MOESI_CMP_directory.py
@@ -80,10 +80,12 @@ def create_system(options, system, piobus, dma_ports, ruby_system):
         #
         l1i_cache = L1Cache(size = options.l1i_size,
                             assoc = options.l1i_assoc,
-                            start_index_bit = block_size_bits)
+                            start_index_bit = block_size_bits,
+                            is_icache = True)
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc,
-                            start_index_bit = block_size_bits)
+                            start_index_bit = block_size_bits,
+                            is_icache = False)
 
         l1_cntrl = L1Cache_Controller(version = i,
                                       cntrl_id = cntrl_count,