mem/cache/cache_builder.cc
+ python/swig/main_wrap.cc
+
sim/builder.cc
sim/debug.cc
sim/eventq.cc
sim/faults.cc
sim/main.cc
- python/swig/cc_main_wrap.cc
sim/param.cc
sim/root.cc
sim/serialize.cc
pyzip_files.append('m5/info.py')
pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py'))
-env.Command(['swig/cc_main_wrap.cc', 'm5/cc_main.py'],
- 'swig/cc_main.i',
+env.Command(['swig/main_wrap.cc', 'm5/internal/main.py'],
+ 'swig/main.i',
'$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
'-o ${TARGETS[0]} $SOURCES')
-pyzip_dep_files.append('m5/cc_main.py')
+pyzip_dep_files.append('m5/internal/main.py')
# Action function to build the zip archive. Uses the PyZipFile module
# included in the standard Python library.
def getCCObject(self):
if not self._ccObject:
self._ccObject = -1 # flag to catch cycles in recursion
- self._ccObject = cc_main.createSimObject(self.path())
+ self._ccObject = internal.main.createSimObject(self.path())
elif self._ccObject == -1:
raise RuntimeError, "%s: recursive call to getCCObject()" \
% self.path()
# i don't know if there's a better way to do this - calling
# setMemoryMode directly from self._ccObject results in calling
# SimObject::setMemoryMode, not the System::setMemoryMode
- system_ptr = cc_main.convertToSystemPtr(self._ccObject)
+ system_ptr = internal.main.convertToSystemPtr(self._ccObject)
system_ptr.setMemoryMode(mode)
for child in self._children.itervalues():
child.changeTiming(mode)
def takeOverFrom(self, old_cpu):
- cpu_ptr = cc_main.convertToBaseCPUPtr(old_cpu._ccObject)
+ cpu_ptr = internal.main.convertToBaseCPUPtr(old_cpu._ccObject)
self._ccObject.takeOverFrom(cpu_ptr)
# generate output file for 'dot' to display as a pretty graph.
# short to avoid polluting other namespaces.
__all__ = ['SimObject', 'ParamContext']
-
# see comment on imports at end of __init__.py.
import proxy
-import cc_main
+import internal
import m5
import atexit, os, sys
# import the SWIG-wrapped main C++ functions
-import cc_main
+import internal
# import a few SWIG-wrapped items (those that are likely to be used
# directly by user scripts) completely into this module for
# convenience
-from cc_main import simulate, SimLoopExitEvent
+from internal.main import simulate, SimLoopExitEvent
# import the m5 compile options
import defines
root.print_ini()
sys.stdout.close() # close config.ini
sys.stdout = sys.__stdout__ # restore to original
- cc_main.loadIniFile(resolveSimObject) # load config.ini into C++
+ internal.main.loadIniFile(resolveSimObject) # load config.ini into C++
root.createCCObject()
root.connectPorts()
- cc_main.finalInit()
+ internal.main.finalInit()
noDot = True # temporary until we fix dot
if not noDot:
dot = pydot.Dot()
# Export curTick to user script.
def curTick():
- return cc_main.cvar.curTick
+ return internal.main.cvar.curTick
# register our C++ exit callback function with Python
-atexit.register(cc_main.doExitCleanup)
+atexit.register(internal.main.doExitCleanup)
# This loops until all objects have been fully drained.
def doDrain(root):
# be drained.
def drain(root):
all_drained = False
- drain_event = cc_main.createCountedDrain()
+ drain_event = internal.main.createCountedDrain()
unready_objects = root.startDrain(drain_event, True)
# If we've got some objects that can't drain immediately, then simulate
if unready_objects > 0:
simulate()
else:
all_drained = True
- cc_main.cleanupCountedDrain(drain_event)
+ internal.main.cleanupCountedDrain(drain_event)
return all_drained
def resume(root):
raise TypeError, "Object is not a root object. Checkpoint must be called on a root object."
doDrain(root)
print "Writing checkpoint"
- cc_main.serializeAll(dir)
+ internal.main.serializeAll(dir)
resume(root)
def restoreCheckpoint(root, dir):
print "Restoring from checkpoint"
- cc_main.unserializeAll(dir)
+ internal.main.unserializeAll(dir)
resume(root)
def changeToAtomic(system):
"called on a root object."
doDrain(system)
print "Changing memory mode to atomic"
- system.changeTiming(cc_main.SimObject.Atomic)
+ system.changeTiming(internal.main.SimObject.Atomic)
def changeToTiming(system):
if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
"called on a root object."
doDrain(system)
print "Changing memory mode to timing"
- system.changeTiming(cc_main.SimObject.Timing)
+ system.changeTiming(internal.main.SimObject.Timing)
def switchCpus(cpuList):
print "switching cpus"
raise TypeError, "%s is not of type BaseCPU" % cpu
# Drain all of the individual CPUs
- drain_event = cc_main.createCountedDrain()
+ drain_event = internal.main.createCountedDrain()
unready_cpus = 0
for old_cpu in old_cpus:
unready_cpus += old_cpu.startDrain(drain_event, False)
if unready_cpus > 0:
drain_event.setCount(unready_cpus)
simulate()
- cc_main.cleanupCountedDrain(drain_event)
+ internal.main.cleanupCountedDrain(drain_event)
# Now all of the CPUs are ready to be switched out
for old_cpu in old_cpus:
old_cpu._ccObject.switchOut()
return opts,args
def main():
- import cc_main
+ import internal
parse_args()
print "M5 Simulator System"
print brief_copyright
print
- print "M5 compiled %s" % cc_main.cvar.compileDate;
+ print "M5 compiled %s" % internal.main.cvar.compileDate;
print "M5 started %s" % datetime.now().ctime()
print "M5 executing on %s" % socket.gethostname()
print "command line:",
usage(2)
# tell C++ about output directory
- cc_main.setOutputDir(options.outdir)
+ internal.main.setOutputDir(options.outdir)
# update the system path with elements from the -p option
sys.path[0:0] = options.path
if self.ccConnected: # already done this
return
peer = self.peer
- cc_main.connectPorts(self.simobj.getCCObject(), self.name, self.index,
- peer.simobj.getCCObject(), peer.name, peer.index)
+ internal.main.connectPorts(self.simobj.getCCObject(), self.name,
+ self.index, peer.simobj.getCCObject(),
+ peer.name, peer.index)
self.ccConnected = True
peer.ccConnected = True
from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
import proxy
import objects
-import cc_main
+import internal
#endif
}
-extern "C" { void init_cc_main(); }
+extern "C" {
+void init_main();
+}
int
main(int argc, char **argv)
Py_Initialize();
PySys_SetArgv(argc, argv);
- // initialize SWIG 'cc_main' module
- init_cc_main();
+ // initialize SWIG 'm5.internal.main' module
+ init_main();
PyRun_SimpleString("import m5.main");
PyRun_SimpleString("m5.main.main()");