2003-06-27 Michael Snyder <msnyder@redhat.com>

        * gencode.c (op tab): Implement movca.l.

diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index ad4bd8fcfa0f8789caf598cf70aab89ae24705c4..2b6624d897333b683adc677007eef4602b922d98 100644 (file)
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -4,6 +4,7 @@
 
 2003-06-27  Michael Snyder  <msnyder@redhat.com>
 
+       * gencode.c (op tab): Implement movca.l.
        * gencode.c (op movsxy_tab): Fix an error in the bit pattern.
        * gencode.c (gensim_caselist): The movy instructions use
        registers R6 and R7 (not R4 and R5 like the movx insns).

diff --git a/sim/sh/gencode.c b/sim/sh/gencode.c
index e8e780fec9f7b8bcf581f025604b6091f78e18cb..ea6d323eab003c2ed75f5a3672b9f4b155a18ac3 100644 (file)
--- a/sim/sh/gencode.c
+++ b/sim/sh/gencode.c
@@ -750,9 +750,10 @@ op tab[] =
     "R0 = ((i + 4 + PH2T (PC)) & ~0x3);",
   },
 
-  { "0", "", "movca.l @R0, <REG_N>", "0000nnnn11000011",
-    "/* FIXME: Not implemented */",
-    "RAISE_EXCEPTION (SIGILL);",
+  { "", "n0", "movca.l R0, @<REG_N>", "0000nnnn11000011",
+    "/* We don't simulate cache, so this insn is identical to mov.  */",
+    "MA (1);",
+    "WLAT (R[n], R[0]);",
   },
 
   { "n", "", "movt <REG_N>", "0000nnnn00101001",