}")
(define_insn ""
- [(set (match_operand:DI 0 "push_operand" "=<,<,<,<")
- (match_operand:DI 1 "general_operand" "riF,o,o,o"))
- (clobber (match_scratch:SI 2 "=X,&r,&r,X"))
- (clobber (match_scratch:SI 3 "=X,&r,X,X"))]
+ [(set (match_operand:DI 0 "push_operand" "=<")
+ (match_operand:DI 1 "general_operand" "riF"))]
""
- "*
-{
- if (GET_CODE (operands[1]) != MEM)
- return output_move_double (operands);
+ "* return output_move_double (operands);")
- else
- return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode), 2, 4);
-}")
+(define_insn ""
+ [(set (match_operand:DI 0 "push_operand" "=<")
+ (match_operand:DI 1 "memory_operand" "o"))]
+ "TARGET_PUSH_MEMORY"
+ "* return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode),0,0);")
-(define_insn "movdi"
- [(set (match_operand:DI 0 "general_operand" "=o,o,r,rm")
- (match_operand:DI 1 "general_operand" "o,o,m,riF"))
- (clobber (match_scratch:SI 2 "=&r,&r,X,X"))
- (clobber (match_scratch:SI 3 "=&r,X,X,X"))]
+(define_expand "movdi"
+ [(set (match_operand:DI 0 "general_operand" "")
+ (match_operand:DI 1 "general_operand" ""))]
""
- "*
+ "
{
- rtx low[2], high[2], xop[6];
-
- if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
- return output_move_double (operands);
- else
- return output_move_memory (operands, insn, GET_MODE_SIZE (DImode), 2, 4);
+ /* Don't generate memory->memory moves, go through a register */
+ if (TARGET_MOVE
+ && (reload_in_progress | reload_completed) == 0
+ && GET_CODE (operands[0]) == MEM
+ && GET_CODE (operands[1]) == MEM)
+ {
+ operands[1] = force_reg (DImode, operands[1]);
+ }
}")
+(define_insn ""
+ [(set (match_operand:DI 0 "general_operand" "=g,r")
+ (match_operand:DI 1 "general_operand" "riF,m"))]
+ "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM)
+ || (GET_CODE (operands[1]) != MEM)"
+ "* return output_move_double (operands);")
+
\f
;;- conversion instructions
;;- NONE