Do not collect disabled $memwr cells

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 6bc4b44caf3362a821a9a3b5f3c20a7ac9bbb672..134b5e8e122823a957f793e7c8c01be9d833e51a 100644 (file)
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -110,21 +110,24 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
                        SigSpec data = sigmap(cell->getPort("\\DATA"));
                        SigSpec en = sigmap(cell->getPort("\\EN"));
 
-                       clk.extend_u0(1, false);
-                       clk_enable.extend_u0(1, false);
-                       clk_polarity.extend_u0(1, false);
-                       addr.extend_u0(addr_bits, false);
-                       data.extend_u0(memory->width, false);
-                       en.extend_u0(memory->width, false);
-
-                       sig_wr_clk.append(clk);
-                       sig_wr_clk_enable.append(clk_enable);
-                       sig_wr_clk_polarity.append(clk_polarity);
-                       sig_wr_addr.append(addr);
-                       sig_wr_data.append(data);
-                       sig_wr_en.append(en);
-
-                       wr_ports++;
+                       if (!en.is_fully_zero())
+                       {
+                               clk.extend_u0(1, false);
+                               clk_enable.extend_u0(1, false);
+                               clk_polarity.extend_u0(1, false);
+                               addr.extend_u0(addr_bits, false);
+                               data.extend_u0(memory->width, false);
+                               en.extend_u0(memory->width, false);
+
+                               sig_wr_clk.append(clk);
+                               sig_wr_clk_enable.append(clk_enable);
+                               sig_wr_clk_polarity.append(clk_polarity);
+                               sig_wr_addr.append(addr);
+                               sig_wr_data.append(data);
+                               sig_wr_en.append(en);
+
+                               wr_ports++;
+                       }
                        continue;
                }