Added StrandStsReg operand.

--HG--
extra : convert_revision : 51be41716ed9fe0e99e53f2341ad5651a525055a

diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index caee20b0c9dacf11bccd0dfac9d066a3c6ab1a27..2d200f568b48d0aba7d4eb9ee060d103a0fc001a 100644 (file)
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -123,6 +123,7 @@ def operands {{
     'Htba':            ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
     'HstickCmpr':      ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
     'Hver':            ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
+    'StrandStsReg':    ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
 
     'Fsr':             ('ControlReg', 'udw', 'MISCREG_FSR', None, 80),
     # Mem gets a large number so it's always last