Rename cycles() function to ticks()

--HG--
extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5

diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index 02e9c92bb33b50c98db87cc452fd3c592af2ab8e..82f284ec4ddee7d536c38479bb94e81344a9cb97 100755 (executable)
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -304,7 +304,7 @@ MiscRegFile::scheduleCP0Update(int delay)
 
         //schedule UPDATE
         CP0Event *cp0_event = new CP0Event(this, cpu, UpdateCP0);
-        cp0_event->schedule(curTick + cpu->cycles(delay));
+        cp0_event->schedule(curTick + cpu->ticks(delay));
     }
 }
 
@@ -364,9 +364,9 @@ void
 MiscRegFile::CP0Event::scheduleEvent(int delay)
 {
     if (squashed())
-        reschedule(curTick + cpu->cycles(delay));
+        reschedule(curTick + cpu->ticks(delay));
     else if (!scheduled())
-        schedule(curTick + cpu->cycles(delay));
+        schedule(curTick + cpu->ticks(delay));
 }
 
 void

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 093e0356b6076ff9e00c22a0ed269e59e565d8bc..b6880ff94735b3a641be8138c030e2be7803f574 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1033,7 +1033,7 @@ doMmuReadError:
             (uint32_t)asi, va);
     }
     pkt->makeAtomicResponse();
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 Tick
@@ -1280,7 +1280,7 @@ doMmuWriteError:
             (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
     }
     pkt->makeAtomicResponse();
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 #endif

diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 48e97a5317bc58531f570031681fdfb5565b1d97..fe733813cd54d167f0ae03d23d3ab5b5f6af1aab 100644 (file)
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -85,7 +85,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(tick_cmpr & ~mask(63)) && time > 0) {
             if (tickCompare->scheduled())
                 tickCompare->deschedule();
-            tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
+            tickCompare->schedule(time * tc->getCpuPtr()->ticks(1));
         }
         panic("writing to TICK compare register %#X\n", val);
         break;
@@ -101,7 +101,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(stick_cmpr & ~mask(63)) && time > 0) {
             if (sTickCompare->scheduled())
                 sTickCompare->deschedule();
-            sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
+            sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick);
         }
         DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
         break;
@@ -171,7 +171,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
         if (!(hstick_cmpr & ~mask(63)) && time > 0) {
             if (hSTickCompare->scheduled())
                 hSTickCompare->deschedule();
-            hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
+            hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1));
         }
         DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
         break;
@@ -315,7 +315,7 @@ MiscRegFile::processSTickCompare(ThreadContext *tc)
             setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
         }
     } else
-        sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
+        sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
 }
 
 void
@@ -341,6 +341,6 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
         }
         // Need to do something to cause interrupt to happen here !!! @todo
     } else
-        hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
+        hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
 }
 

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ad23cb7e4985286a58d4212effa12c56aa0133ad..d7f9e6665b48c20b248be08d7da243b56311a34d 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -95,13 +95,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 Tick
 DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 Tick
 DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
 {
-    return tc->getCpuPtr()->cycles(1);
+    return tc->getCpuPtr()->ticks(1);
 }
 
 #endif

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 7b31eb7667a0361414ac12b22b089f0931cdb0ff..25bd3f893f56c96e3e5d5622bbfdaf85a7c2416d 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -74,7 +74,7 @@ CPUProgressEvent::process()
 {
     Counter temp = cpu->totalInstructions();
 #ifndef NDEBUG
-    double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1));
+    double ipc = double(temp - lastNumInst) / (interval / cpu->ticks(1));
 
     DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
              cpu->name(), temp - lastNumInst, ipc);
@@ -223,7 +223,7 @@ BaseCPU::startup()
 
     if (params->progress_interval) {
         new CPUProgressEvent(&mainEventQueue,
-                             cycles(params->progress_interval),
+                             ticks(params->progress_interval),
                              this);
     }
 }

diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 6f4158d47171ede30db021f08742bce475e9e63c..3c3e9152370edde2c1f213b9b686df9a05b067de 100644 (file)
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -82,7 +82,7 @@ class BaseCPU : public MemObject
   public:
 //    Tick currentTick;
     inline Tick frequency() const { return Clock::Frequency / clock; }
-    inline Tick cycles(int numCycles) const { return clock * numCycles; }
+    inline Tick ticks(int numCycles) const { return clock * numCycles; }
     inline Tick curCycle() const { return curTick / clock; }
     inline Tick tickToCycles(Tick val) const { return val / clock; }
     // @todo remove me after debugging with legion done

diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 583fd5f8d7abaa532714e9bd040ca7e6b22cd1a8..f8c8a0547d82bebe4aeea7c9227a5153af2a2722 100644 (file)
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -270,7 +270,7 @@ void
 MemTest::tick()
 {
     if (!tickEvent.scheduled())
-        tickEvent.schedule(curTick + cycles(1));
+        tickEvent.schedule(curTick + ticks(1));
 
     if (++noResponseCycles >= 500000) {
         cerr << name() << ": deadlocked at cycle " << curTick << endl;

diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index fa168c70bce1cfeb8eee903f869d54dc1b877dc7..1c918df330ba2776da9bec9c994da5a66cd62bc7 100644 (file)
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -55,7 +55,7 @@ class MemTest : public MemObject
     // register statistics
     virtual void regStats();
 
-    inline Tick cycles(int numCycles) const { return numCycles; }
+    inline Tick ticks(int numCycles) const { return numCycles; }
 
     // main simulation loop (one cycle)
     void tick();

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index f263383aef0ec13998d086c34ba8b9ab80bff263..e32dc79215f1fbc35c24a29ad5db095573c7fc1a 100644 (file)
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -325,7 +325,7 @@ DefaultCommit<Impl>::initStage()
     cpu->activateStage(O3CPU::CommitIdx);
 
     cpu->activityThisCycle();
-    trapLatency = cpu->cycles(trapLatency);
+    trapLatency = cpu->ticks(trapLatency);
 }
 
 template <class Impl>

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b2b7e09c09fae36e48197cd20c4eb67b35d16ec6..3842d27bdab0b0ac96d051a58a1ac93caaafb361 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -464,7 +464,7 @@ FullO3CPU<Impl>::tick()
             lastRunningCycle = curTick;
             timesIdled++;
         } else {
-            tickEvent.schedule(nextCycle(curTick + cycles(1)));
+            tickEvent.schedule(nextCycle(curTick + ticks(1)));
             DPRINTF(O3CPU, "Scheduling next tick!\n");
         }
     }
@@ -558,7 +558,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
     // Needs to set each stage to running as well.
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
-                "on cycle %d\n", tid, curTick + cycles(delay));
+                "on cycle %d\n", tid, curTick + ticks(delay));
         scheduleActivateThreadEvent(tid, delay);
     } else {
         activateThread(tid);
@@ -585,7 +585,7 @@ FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
     // Schedule removal of thread data from CPU
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to deallocate "
-                "on cycle %d\n", tid, curTick + cycles(delay));
+                "on cycle %d\n", tid, curTick + ticks(delay));
         scheduleDeallocateContextEvent(tid, remove, delay);
         return false;
     } else {

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index d97a2080ddfb1171325f4e66b5aece4c9f0a7b2a..162e377e1affcf5d33250fa7dd6b5cb9e4533d1a 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -146,9 +146,9 @@ class FullO3CPU : public BaseO3CPU
     void scheduleTickEvent(int delay)
     {
         if (tickEvent.squashed())
-            tickEvent.reschedule(nextCycle(curTick + cycles(delay)));
+            tickEvent.reschedule(nextCycle(curTick + ticks(delay)));
         else if (!tickEvent.scheduled())
-            tickEvent.schedule(nextCycle(curTick + cycles(delay)));
+            tickEvent.schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule tick event, regardless of its current state. */
@@ -187,10 +187,10 @@ class FullO3CPU : public BaseO3CPU
         // Schedule thread to activate, regardless of its current state.
         if (activateThreadEvent[tid].squashed())
             activateThreadEvent[tid].
-                reschedule(nextCycle(curTick + cycles(delay)));
+                reschedule(nextCycle(curTick + ticks(delay)));
         else if (!activateThreadEvent[tid].scheduled())
             activateThreadEvent[tid].
-                schedule(nextCycle(curTick + cycles(delay)));
+                schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule actiavte thread event, regardless of its current state. */
@@ -238,10 +238,10 @@ class FullO3CPU : public BaseO3CPU
         // Schedule thread to activate, regardless of its current state.
         if (deallocateContextEvent[tid].squashed())
             deallocateContextEvent[tid].
-                reschedule(nextCycle(curTick + cycles(delay)));
+                reschedule(nextCycle(curTick + ticks(delay)));
         else if (!deallocateContextEvent[tid].scheduled())
             deallocateContextEvent[tid].
-                schedule(nextCycle(curTick + cycles(delay)));
+                schedule(nextCycle(curTick + ticks(delay)));
     }
 
     /** Unschedule thread deallocation in CPU */

diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 47f019ebe26e83f0d377ee15699ffe87f5d780a1..aea62f12d3fe7b924e328cae167ce978999245cf 100644 (file)
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -752,7 +752,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
                 FUCompletion *execution = new FUCompletion(issuing_inst,
                                                            idx, this);
 
-                execution->schedule(curTick + cpu->cycles(issue_latency - 1));
+                execution->schedule(curTick + cpu->ticks(issue_latency - 1));
 
                 // @todo: Enforce that issue_latency == 1 or op_latency
                 if (issue_latency > 1) {

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 78d0892c4118466e2464deca1425c04368151671..036db13516f5392d023a47ee8d0bf7deab25bd55 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -315,9 +315,9 @@ class OzoneCPU : public BaseCPU
     void scheduleTickEvent(int delay)
     {
         if (tickEvent.squashed())
-            tickEvent.reschedule(curTick + cycles(delay));
+            tickEvent.reschedule(curTick + ticks(delay));
         else if (!tickEvent.scheduled())
-            tickEvent.schedule(curTick + cycles(delay));
+            tickEvent.schedule(curTick + ticks(delay));
     }
 
     /// Unschedule tick event, regardless of its current state.

diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 37a91c6305abe1f508de5ff2eba59a9d1074b52c..5080c54f65e4361ce9fb6bff0261879cc4e76856 100644 (file)
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -613,7 +613,7 @@ OzoneCPU<Impl>::tick()
     comInstEventQueue[0]->serviceEvents(numInst);
 
     if (!tickEvent.scheduled() && _status == Running)
-        tickEvent.schedule(curTick + cycles(1));
+        tickEvent.schedule(curTick + ticks(1));
 }
 
 template <class Impl>

diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index f84bda3485e0705b9995b421d250531ac77199e9..42788cee142693514a9dc6bd98d13a5e18d184cb 100644 (file)
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -45,7 +45,7 @@ LWBackEnd<Impl>::generateTrapEvent(Tick latency)
 
     TrapEvent *trap = new TrapEvent(this);
 
-    trap->schedule(curTick + cpu->cycles(latency));
+    trap->schedule(curTick + cpu->ticks(latency));
 
     thread->trapPending = true;
 }

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 06f52e30ea9e449b9ca78d1094fb2c5354e4a38d..9187fa7c7916a624b6dc9dfeb0c4bb7706700131 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -254,7 +254,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay)
     notIdleFraction++;
 
     //Make sure ticks are still on multiples of cycles
-    tickEvent.schedule(nextCycle(curTick + cycles(delay)));
+    tickEvent.schedule(nextCycle(curTick + ticks(delay)));
     _status = Running;
 }
 
@@ -584,7 +584,7 @@ AtomicSimpleCPU::tick()
 {
     DPRINTF(SimpleCPU, "Tick\n");
 
-    Tick latency = cycles(1); // instruction takes one cycle by default
+    Tick latency = ticks(1); // instruction takes one cycle by default
 
     for (int i = 0; i < width; ++i) {
         numCycles++;
@@ -642,14 +642,14 @@ AtomicSimpleCPU::tick()
 
             if (simulate_stalls) {
                 Tick icache_stall =
-                    icache_access ? icache_latency - cycles(1) : 0;
+                    icache_access ? icache_latency - ticks(1) : 0;
                 Tick dcache_stall =
-                    dcache_access ? dcache_latency - cycles(1) : 0;
-                Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
-                if (cycles(stall_cycles) < (icache_stall + dcache_stall))
-                    latency += cycles(stall_cycles+1);
+                    dcache_access ? dcache_latency - ticks(1) : 0;
+                Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
+                if (ticks(stall_cycles) < (icache_stall + dcache_stall))
+                    latency += ticks(stall_cycles+1);
                 else
-                    latency += cycles(stall_cycles);
+                    latency += ticks(stall_cycles);
             }
 
         }

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index eee5b8cb514b9eea5d0e214ed5eda93537627975..2b5577e04e8cc0dd0b57f3020b93d5b71c85763b 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -222,7 +222,7 @@ TimingSimpleCPU::activateContext(int thread_num, int delay)
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
+    fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay)));
 }
 
 

diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index e5739b2ce4238ba5b24abff5651751d94b422ce5..d3cf34e9d86faaef78efb8d50c2910a67d40cd3a 100644 (file)
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -110,10 +110,10 @@ TraceCPU::tick()
         if (mainEventQueue.empty()) {
             exitSimLoop("end of memory trace reached");
         } else {
-            tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
+            tickEvent.schedule(mainEventQueue.nextEventTime() + ticks(1));
         }
     } else {
-        tickEvent.schedule(max(curTick + cycles(1), nextCycle));
+        tickEvent.schedule(max(curTick + ticks(1), nextCycle));
     }
 }
 

diff --git a/src/cpu/trace/trace_cpu.hh b/src/cpu/trace/trace_cpu.hh
index 9c96d71d53cd4de9cbc2717fedf9b8dec24e8a05..b88c7072e23083700856ea01f87d62e14ee4cc4a 100644 (file)
--- a/src/cpu/trace/trace_cpu.hh
+++ b/src/cpu/trace/trace_cpu.hh
@@ -107,7 +107,7 @@ class TraceCPU : public SimObject
              MemInterface *dcache_interface,
              MemTraceReader *data_trace);
 
-    inline Tick cycles(int numCycles) { return numCycles; }
+    inline Tick ticks(int numCycles) { return numCycles; }
 
     /**
      * Perform all the accesses for one cycle.

diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 84882b0565e5b78b9a92863a627ec5a653c1c368..460f6a9fb008041b55e33f55ca6b741269c0dfd4 100644 (file)
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -1104,7 +1104,7 @@ IGbE::restartClock()
 {
     if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) && getState() ==
             SimObject::Running)
-        tickEvent.schedule((curTick/cycles(1)) * cycles(1) + cycles(1));
+        tickEvent.schedule((curTick/ticks(1)) * ticks(1) + ticks(1));
 }
 
 unsigned int
@@ -1400,7 +1400,7 @@ IGbE::tick()
 
 
     if (rxTick || txTick || txFifoTick)
-        tickEvent.schedule(curTick + cycles(1));
+        tickEvent.schedule(curTick + ticks(1));
 }
 
 void

diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index cbe7cf8c0856c887c571ff27e9d3787b7d368748..30aa6430e9de593e46c73699bdde3a38b702c1ea 100644 (file)
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -614,7 +614,7 @@ class IGbE : public EtherDevice
     virtual EtherInt *getEthPort(const std::string &if_name, int idx);
 
     Tick clock;
-    inline Tick cycles(int numCycles) const { return numCycles * clock; }
+    inline Tick ticks(int numCycles) const { return numCycles * clock; }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);

diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 0788b89a94de45f81d0dee06e247529ab5dd1090..bd48bdca577845b89b01b1391a409fe9f47adb57 100644 (file)
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -1469,7 +1469,7 @@ NSGigE::rxKick()
         }
 
         // Go to the next state machine clock tick.
-        rxKickTick = curTick + cycles(1);
+        rxKickTick = curTick + ticks(1);
     }
 
     switch(rxDmaState) {
@@ -1916,7 +1916,7 @@ NSGigE::txKick()
         }
 
         // Go to the next state machine clock tick.
-        txKickTick = curTick + cycles(1);
+        txKickTick = curTick + ticks(1);
     }
 
     switch(txDmaState) {
@@ -2322,7 +2322,7 @@ NSGigE::transferDone()
 
     DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
 
-    txEvent.reschedule(curTick + cycles(1), true);
+    txEvent.reschedule(curTick + ticks(1), true);
 }
 
 bool

diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh
index 5e589687aa3f8f3f7cc55cae9e115ee4a04d953c..dfdd81b66c74b11adb854fbcf919e13c2756750f 100644 (file)
--- a/src/dev/ns_gige.hh
+++ b/src/dev/ns_gige.hh
@@ -199,7 +199,7 @@ class NSGigE : public EtherDevice
 
     /* state machine cycle time */
     Tick clock;
-    inline Tick cycles(int numCycles) const { return numCycles * clock; }
+    inline Tick ticks(int numCycles) const { return numCycles * clock; }
 
     /* tx State Machine */
     TxState txState;

diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index 7457a2b471a7719edb959bfd46f58c5f62dd7696..c63966528c2be60830a672daf4fea6819936ad7e 100644 (file)
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -1211,7 +1211,7 @@ Device::transferDone()
 
     DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
 
-    txEvent.reschedule(curTick + cycles(1), true);
+    txEvent.reschedule(curTick + ticks(1), true);
 }
 
 bool

diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh
index 469b281917c3c5f114c888d901797e9866287917..e85d93fe471154ed8aaa6cc25fedd892f5ada9ed 100644 (file)
--- a/src/dev/sinic.hh
+++ b/src/dev/sinic.hh
@@ -51,7 +51,7 @@ class Base : public PciDev
     bool rxEnable;
     bool txEnable;
     Tick clock;
-    inline Tick cycles(int numCycles) const { return numCycles * clock; }
+    inline Tick ticks(int numCycles) const { return numCycles * clock; }
 
   protected:
     Tick intrDelay;

diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 10127aa5ff407959afea48d0ca9da3e35ba15360..157d39e9318bb73248f7281ff5cc3ce0023b7843 100644 (file)
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -105,7 +105,7 @@ namespace PseudoInst
 
         EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
 
-        Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
+        Tick resume = curTick + tc->getCpuPtr()->ticks(cycles);
 
         quiesceEvent->reschedule(resume, true);