soc/cores/spi_flash: add missing endianness parameter

diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py
index 86cab3ee1d11ea37c69e7d4fefde3c7330f22479..35d2ac44786bc616d120ea00f639bda20db07bfc 100644 (file)
--- a/litex/soc/cores/spi_flash.py
+++ b/litex/soc/cores/spi_flash.py
@@ -117,7 +117,7 @@ class SpiFlashDualQuad(Module, AutoCSR):
 
 
 class SpiFlashSingle(Module, AutoCSR):
-    def __init__(self, pads, dummy=15, div=2):
+    def __init__(self, pads, dummy=15, div=2, endianness="big"):
         """
         Simple SPI flash.
         Supports 1-bit reads. Only supports mode0 (cpol=0, cpha=0).