Tidy up, fix for -nosrl

diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index 3d5f7877065f913adb7f1b269f127937bb268a82..c61fd7070eeba8ce481246412990808aa482ea8e 100644 (file)
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -22,21 +22,26 @@
 
 `ifndef _NO_FFS
 
+`ifndef _NO_POS_SR
 module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
 module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
 
 module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_         _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
 module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_         _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
 module  \$_DFF_PP0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
 
-module  \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1          _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
 module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1          _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
+`endif
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_         _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_         _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
+
+module  \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1          _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1          _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C),              .R(~R)); endmodule
+`endif
 
 `endif
 

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index a9e50329ca143e0f400bd35e426d2c1dce55248c..e84a6714baea2b22161d3f102177d3824a60ab36 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -116,8 +116,7 @@ struct SynthXilinxPass : public Pass
                log("        pmux2shiftx (without '-nosrl' only)\n");
                log("        opt_expr -mux_undef (without '-nosrl' only)\n");
                log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
-               log("        opt -full\n");
-               log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
+               log("        techmap -map +/xilinx/arith_map.v\n");
                log("        opt -fast\n");
                log("\n");
                log("    map_cells:\n");
@@ -125,7 +124,8 @@ struct SynthXilinxPass : public Pass
                log("        clean\n");
                log("\n");
                log("    map_luts:\n");
-               log("        techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?\n");
+               log("        opt -full\n");
+               log("        techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
                log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
                log("        clean\n");
                log("        shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
@@ -282,12 +282,10 @@ struct SynthXilinxPass : public Pass
                                Pass::call(design, "shregmap -tech xilinx -minlen 3");
                        }
 
-                       Pass::call(design, "opt -full");
-
                        if (vpr) {
-                               Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
+                               Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
                        } else {
-                               Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
+                               Pass::call(design, "techmap -map +/xilinx/arith_map.v");
                        }
 
                        Pass::call(design, "hierarchy -check");
@@ -302,7 +300,8 @@ struct SynthXilinxPass : public Pass
 
                if (check_label(active, run_from, run_to, "map_luts"))
                {
-                       Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/ff_map.v t:$_DFF_?N?");
+                       Pass::call(design, "opt -full");
+                       Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
                        Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
                        Pass::call(design, "clean");
                        if (!nosrl)