aarch64: Fix PSEL opcode mask

The opcode mask for PSEL was missing some bits, which meant
that some upcoming SME2 opcodes would be misinterpreted as PSELs.

diff --git a/gas/testsuite/gas/aarch64/sme-9.d b/gas/testsuite/gas/aarch64/sme-9.d
index ef314c61451705ae10bbc10f54fc000fec1fe8ad..9a6175c390609d4ba5fdfaeefb9785964251640b 100644 (file)
--- a/gas/testsuite/gas/aarch64/sme-9.d
+++ b/gas/testsuite/gas/aarch64/sme-9.d
@@ -71,3 +71,6 @@ Disassembly of section \.text:
   f4:  44cbc544        uclamp  z4.d, z10.d, z11.d
   f8:  25277c61        psel    p1, p15, p3.b\[w15, 0\]
   fc:  252778a2        psel    p2, p14, p5.b\[w15, 0\]
+ 100:  25244200        \.inst  0x25244200 ; undefined
+ 104:  25244010        \.inst  0x25244010 ; undefined
+ 108:  25244210        \.inst  0x25244210 ; undefined

diff --git a/gas/testsuite/gas/aarch64/sme-9.s b/gas/testsuite/gas/aarch64/sme-9.s
index be8511fe3dfb6d3ca7893f9a9afbfec82ba8b8e1..495a7f9fbf0820ea85a206af9d17c554f4451461 100644 (file)
--- a/gas/testsuite/gas/aarch64/sme-9.s
+++ b/gas/testsuite/gas/aarch64/sme-9.s
@@ -84,3 +84,8 @@ foo .req p1
 bar .req w15
 psel foo, p15, p3.b[w15, 0]
 psel p2, p14, p5.b[bar, 0]
+
+// These were previously incorrectly decoded as PSELs.
+.inst 0x25244200
+.inst 0x25244010
+.inst 0x25244210

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 6970365047139509818f9b2cfb876948d2ca3935..96e6c13628211ed60f7f754ed2feba2bbdcefcdd 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
   SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
   SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-  SME_INSN ("psel", 0x25204000, 0xff20c000, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+  SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
 
   /* SIMD Dot Product (optional in v8.2-A).  */
   DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),