mibuild/xilinx: remove obsolete CRG_DS

diff --git a/mibuild/xilinx/common.py b/mibuild/xilinx/common.py
index 9b5d994344cc4ff5c87f96707e1cc6927e4112e5..a7b1175c40736c1995d7124dc397a5dadf77b01d 100644 (file)
--- a/mibuild/xilinx/common.py
+++ b/mibuild/xilinx/common.py
@@ -29,22 +29,6 @@ def settings(path, ver=None, sub=None):
 
        raise OSError("no settings file found")
 
-class CRG_DS(Module):
-       def __init__(self, platform, clk_name, rst_name, rst_invert=False):
-               reset_less = rst_name is None
-               self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
-               self._clk = platform.request(clk_name)
-               self.specials += Instance("IBUFGDS",
-                       Instance.Input("I", self._clk.p),
-                       Instance.Input("IB", self._clk.n),
-                       Instance.Output("O", self.cd_sys.clk)
-               )
-               if not reset_less:
-                       if rst_invert:
-                               self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
-                       else:
-                               self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
-
 class XilinxNoRetimingImpl(Module):
        def __init__(self, reg):
                self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)