#
# Authors: Gabe Black
+from m5.defines import buildEnv
from m5.params import *
+from m5.proxy import *
from Device import BasicPioDevice
class X86LocalApic(BasicPioDevice):
int_port = Port("Port for sending and receiving interrupt messages")
int_latency = Param.Latency('1ns', \
"Latency for an interrupt to propagate through this device.")
+ if buildEnv['FULL_SYSTEM']: # No platform in SE mode.
+ platform = Param.Platform(Parent.any,
+ "Platform this device is part of.")
//
BasicPioDevice::init();
IntDev::init();
-
+#if FULL_SYSTEM
Pc * pc = dynamic_cast<Pc *>(platform);
assert(pc);
pc->southBridge->ioApic->registerLocalApic(initialApicId, this);
+#endif
}
pendingStartup(false), startupVector(0),
startedUp(false), pendingUnmaskableInt(false),
pendingIPIs(0), cpu(NULL)
+#if FULL_SYSTEM
+ , platform(p->platform)
+#endif
{
pioSize = PageBytes;
memset(regs, 0, sizeof(regs));
#include "arch/x86/faults.hh"
#include "arch/x86/intmessage.hh"
#include "base/bitfield.hh"
+#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "dev/x86/intdev.hh"
#include "dev/io_device.hh"
int initialApicId;
+#if FULL_SYSTEM
+ Platform *platform;
+#endif
+
public:
/*
* Params stuff.
type = 'PioDevice'
abstract = True
pio = Port("Programmed I/O port")
- platform = Param.Platform(Parent.any, "Platform this device is part of")
system = Param.System(Parent.any, "System this device is part of")
class BasicPioDevice(PioDevice):
class PciConfigAll(PioDevice):
type = 'PciConfigAll'
+ platform = Param.Platform(Parent.any, "Platform this device is part of.")
pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
bus = Param.UInt8(0x00, "PCI bus to act as config space for")
size = Param.MemorySize32('16MB', "Size of config space")
class PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
+ platform = Param.Platform(Parent.any, "Platform this device is part of.")
config = Port(Self.pio.peerObj.port, "PCI configuration space port")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
class Uart(BasicPioDevice):
type = 'Uart'
abstract = True
+ platform = Param.Platform(Parent.any, "Platform this device is part of.")
terminal = Param.Terminal(Parent.any, "The terminal")
class Uart8250(Uart):
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
disk = Param.SimpleDisk("Simple Disk")
terminal = Param.Terminal(Parent.any, "The console terminal")
+ platform = Param.Platform(Parent.any, "Platform this device is part of.")
if buildEnv['FULL_SYSTEM']: # No AlphaSystem in SE mode.
system = Param.AlphaSystem(Parent.any, "system object")
class Gic(PioDevice):
type = 'Gic'
+ platform = Param.Platform(Parent.any, "Platform this device is part of.")
dist_addr = Param.Addr(0x1f001000, "Address for distributor")
cpu_addr = Param.Addr(0x1f000100, "Address for cpu")
dist_pio_delay = Param.Latency('10ns', "Delay for PIO r/w to distributor")
#include "mem/packet_access.hh"
Gic::Gic(const Params *p)
- : PioDevice(p),distAddr(p->dist_addr), cpuAddr(p->cpu_addr),
- distPioDelay(p->dist_pio_delay), cpuPioDelay(p->cpu_pio_delay),
- intLatency(p->int_latency), enabled(false), itLines(p->it_lines)
+ : PioDevice(p), platform(p->platform), distAddr(p->dist_addr),
+ cpuAddr(p->cpu_addr), distPioDelay(p->dist_pio_delay),
+ cpuPioDelay(p->cpu_pio_delay), intLatency(p->int_latency),
+ enabled(false), itLines(p->it_lines)
{
itLinesLog2 = ceilLog2(itLines);
Bitfield<12,10> cpu_id;
EndBitUnion(IAR)
+ Platform *platform;
+
/** Distributor address GIC listens at */
Addr distAddr;
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "dev/baddev.hh"
-#include "dev/platform.hh"
#include "mem/port.hh"
#include "params/BadDevice.hh"
#include "sim/system.hh"
PioDevice::PioDevice(const Params *p)
- : MemObject(p), platform(p->platform), sys(p->system), pioPort(NULL)
+ : MemObject(p), sys(p->system), pioPort(NULL)
{}
PioDevice::~PioDevice()
#include "sim/sim_object.hh"
class Event;
-class Platform;
class PioDevice;
class DmaDevice;
class System;
class PioDevice : public MemObject
{
protected:
-
- /** The platform we are in. This is used to decide what type of memory
- * transaction we should perform. */
- Platform *platform;
-
System *sys;
/** The pioPort that handles the requests for us and provides us requests
PciDev::PciDev(const Params *p)
- : DmaDevice(p), plat(p->platform), pioDelay(p->pio_latency),
+ : DmaDevice(p), platform(p->platform), pioDelay(p->pio_latency),
configDelay(p->config_latency), configPort(NULL)
{
config.vendor = htole(p->VendorID);
}
}
- plat->registerPciDevice(p->pci_bus, p->pci_dev, p->pci_func,
+ platform->registerPciDevice(p->pci_bus, p->pci_dev, p->pci_func,
letoh(config.interruptLine));
}
}
protected:
- Platform *plat;
+ Platform *platform;
Tick pioDelay;
Tick configDelay;
PciConfigPort *configPort;
public:
Addr pciToDma(Addr pciAddr) const
- { return plat->pciToDma(pciAddr); }
+ { return platform->pciToDma(pciAddr); }
void
intrPost()
- { plat->postPciInt(letoh(config.interruptLine)); }
+ { platform->postPciInt(letoh(config.interruptLine)); }
void
intrClear()
- { plat->clearPciInt(letoh(config.interruptLine)); }
+ { platform->clearPciInt(letoh(config.interruptLine)); }
uint8_t
interruptLine()
class Iob(PioDevice):
type = 'Iob'
+ platform = Param.Platform(Parent.any, "Platform this device is part of.")
pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
pioDelay = p->pio_latency;
- // Get the interrupt controller from the platform
- ic = platform->intrctrl;
-
for (int x = 0; x < NumDeviceIds; ++x) {
intMan[x].cpu = 0;
intMan[x].vector = 0;