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vector.md (vector_ne_<mode>_p): Correct operand numbers.
authorBill Schmidt <wschmidt@linux.vnet.ibm.com>
Thu, 2 Mar 2017 19:17:04 +0000 (19:17 +0000)
committerWilliam Schmidt <wschmidt@gcc.gnu.org>
Thu, 2 Mar 2017 19:17:04 +0000 (19:17 +0000)
2017-03-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

* config/rs6000/vector.md (vector_ne_<mode>_p): Correct operand
numbers.
(vector_ae_<mode>_p): Likewise.
(vector_nez_<mode>_p): Likewise.
(vector_ne_v2di_p): Likewise.
(vector_ae_v2di_p): Likewise.
(vector_ne_<mode>_p): Likewise.
* config/rs6000/vsx.md (vsx_tsqrt<mode>2_fg): Correct operand
numbers.
(vsx_tsqrt<mode>2_fe): Likewise.

From-SVN: r245849

gcc/ChangeLog patch | blob | history
gcc/config/rs6000/vector.md patch | blob | history
gcc/config/rs6000/vsx.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 85cfb5235e03db4762d7bab1ed0676b9c9585805..c8b375ecf5c00ed6aa7a5c9f60ecf5352fd1f676 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2017-03-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+       * config/rs6000/vector.md (vector_ne_<mode>_p): Correct operand
+       numbers.
+       (vector_ae_<mode>_p): Likewise.
+       (vector_nez_<mode>_p): Likewise.
+       (vector_ne_v2di_p): Likewise.
+       (vector_ae_v2di_p): Likewise.
+       (vector_ne_<mode>_p): Likewise.
+       * config/rs6000/vsx.md (vsx_tsqrt<mode>2_fg): Correct operand
+       numbers.
+       (vsx_tsqrt<mode>2_fe): Likewise.
+
 2017-03-02  Uros Bizjak  <ubizjak@gmail.com>
 
        PR target/79514
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index ef6bd14b2b1a4a71d89468937fefae6dbceacd46..fefe5db6aae101d41d380b085e87015ec82be505 100644 (file)
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -700,7 +700,7 @@
          (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
                             (match_operand:VI 2 "vlogical_operand"))]
           UNSPEC_PREDICATE))
-     (set (match_dup 4)
+     (set (match_dup 3)
          (ne:VI (match_dup 1)
                 (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
@@ -708,7 +708,7 @@
               (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
-  operands[4] = gen_reg_rtx (<MODE>mode);
+  operands[3] = gen_reg_rtx (<MODE>mode);
 })
 
 ;; This expansion handles the V16QI, V8HI, and V4SI modes in the
@@ -719,7 +719,7 @@
          (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
                             (match_operand:VI 2 "vlogical_operand"))]
           UNSPEC_PREDICATE))
-     (set (match_dup 4)
+     (set (match_dup 3)
          (ne:VI (match_dup 1)
                 (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
@@ -730,7 +730,7 @@
                (const_int 1)))]
   "TARGET_P9_VECTOR"
 {
-  operands[4] = gen_reg_rtx (<MODE>mode);
+  operands[3] = gen_reg_rtx (<MODE>mode);
 })
 
 ;; This expansion handles the V16QI, V8HI, and V4SI modes in the
@@ -763,7 +763,7 @@
          (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
                             (match_operand:V2DI 2 "vlogical_operand"))]
                     UNSPEC_PREDICATE))
-     (set (match_dup 4)
+     (set (match_dup 3)
          (eq:V2DI (match_dup 1)
                   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
@@ -771,7 +771,7 @@
               (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
-  operands[4] = gen_reg_rtx (V2DImode);
+  operands[3] = gen_reg_rtx (V2DImode);
 })
 
 ;; This expansion handles the V2DI mode in the implementation of the
@@ -786,7 +786,7 @@
          (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
                             (match_operand:V2DI 2 "vlogical_operand"))]
                     UNSPEC_PREDICATE))
-     (set (match_dup 4)
+     (set (match_dup 3)
          (eq:V2DI (match_dup 1)
                   (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
@@ -797,7 +797,7 @@
                (const_int 1)))]
   "TARGET_P9_VECTOR"
 {
-  operands[4] = gen_reg_rtx (V2DImode);
+  operands[3] = gen_reg_rtx (V2DImode);
 })
 
 ;; This expansion handles the V4SF and V2DF modes in the Power9
@@ -811,7 +811,7 @@
          (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
                             (match_operand:VEC_F 2 "vlogical_operand"))]
                     UNSPEC_PREDICATE))
-     (set (match_dup 4)
+     (set (match_dup 3)
          (eq:VEC_F (match_dup 1)
                    (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
@@ -819,7 +819,7 @@
               (const_int 0)))]
   "TARGET_P9_VECTOR"
 {
-  operands[4] = gen_reg_rtx (<MODE>mode);
+  operands[3] = gen_reg_rtx (<MODE>mode);
 })
 
 ;; This expansion handles the V4SF and V2DF modes in the Power9
@@ -833,7 +833,7 @@
          (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
                             (match_operand:VEC_F 2 "vlogical_operand"))]
                     UNSPEC_PREDICATE))
-     (set (match_dup 4)
+     (set (match_dup 3)
          (eq:VEC_F (match_dup 1)
                    (match_dup 2)))])
    (set (match_operand:SI 0 "register_operand" "=r")
@@ -844,7 +844,7 @@
                (const_int 1)))]
   "TARGET_P9_VECTOR"
 {
-  operands[4] = gen_reg_rtx (<MODE>mode);
+  operands[3] = gen_reg_rtx (<MODE>mode);
 })
 
 (define_expand "vector_gt_<mode>_p"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 111c2e8214bd26661f2a5fd1fccc50e9806cfc48..aabc8f61ecef620b350c5c09e7aa6a6bf9b673a5 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1383,28 +1383,28 @@
 
 ;; *tsqrt* returning the fg flag
 (define_expand "vsx_tsqrt<mode>2_fg"
-  [(set (match_dup 3)
+  [(set (match_dup 2)
        (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
                     UNSPEC_VSX_TSQRT))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-       (gt:SI (match_dup 3)
+       (gt:SI (match_dup 2)
               (const_int 0)))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 {
-  operands[3] = gen_reg_rtx (CCFPmode);
+  operands[2] = gen_reg_rtx (CCFPmode);
 })
 
 ;; *tsqrt* returning the fe flag
 (define_expand "vsx_tsqrt<mode>2_fe"
-  [(set (match_dup 3)
+  [(set (match_dup 2)
        (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
                     UNSPEC_VSX_TSQRT))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
-       (eq:SI (match_dup 3)
+       (eq:SI (match_dup 2)
               (const_int 0)))]
   "VECTOR_UNIT_VSX_P (<MODE>mode)"
 {
-  operands[3] = gen_reg_rtx (CCFPmode);
+  operands[2] = gen_reg_rtx (CCFPmode);
 })
 
 (define_insn "*vsx_tsqrt<mode>2_internal"