Rename MTFSR/MFFSR to FSSR/FRSR

diff --git a/riscv/disasm.cc b/riscv/disasm.cc
index 570ed658f574ab42269971ecba04379360aac1d9..105df75d2a6c3bd12639a80fcf7b9560997f2f95 100644 (file)
--- a/riscv/disasm.cc
+++ b/riscv/disasm.cc
@@ -624,9 +624,9 @@ disassembler::disassembler()
   DEFINE_FXTYPE(flt_d);
   DEFINE_FXTYPE(fle_d);
 
-  add_insn(new disasm_insn_t("mtfsr", match_mtfsr, mask_mtfsr | mask_rd, xrs1_reg));
-  add_insn(new disasm_insn_t("mtfsr", match_mtfsr, mask_mtfsr, xrd_reg, xrs1_reg));
-  DEFINE_DTYPE(mffsr);
+  add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr | mask_rd, xrs1_reg));
+  add_insn(new disasm_insn_t("fssr", match_fssr, mask_fssr, xrd_reg, xrs1_reg));
+  DEFINE_DTYPE(frsr);
 
   // provide a default disassembly for all instructions as a fallback
   #define DECLARE_INSN(code, match, mask) \

diff --git a/riscv/insns/frsr.h b/riscv/insns/frsr.h
new file mode 100644 (file)
index 0000000..29debc4
--- /dev/null
+++ b/riscv/insns/frsr.h
@@ -0,0 +1,2 @@
+require_fp;
+RD = fsr;

diff --git a/riscv/insns/fssr.h b/riscv/insns/fssr.h
new file mode 100644 (file)
index 0000000..cc6f9ea
--- /dev/null
+++ b/riscv/insns/fssr.h
@@ -0,0 +1,4 @@
+require_fp;
+uint32_t tmp = fsr;
+set_fsr(RS1);
+RD = tmp;

diff --git a/riscv/insns/mffsr.h b/riscv/insns/mffsr.h
deleted file mode 100644 (file)
index 29debc4..0000000
--- a/riscv/insns/mffsr.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-RD = fsr;

diff --git a/riscv/insns/mtfsr.h b/riscv/insns/mtfsr.h
deleted file mode 100644 (file)
index cc6f9ea..0000000
--- a/riscv/insns/mtfsr.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-uint32_t tmp = fsr;
-set_fsr(RS1);
-RD = tmp;

diff --git a/riscv/opcodes.h b/riscv/opcodes.h
index 90565e0c892ea1bee997c07d717d2ec044b28668..5e366cd726de59ece5102511b68613824d6d97da 100644 (file)
--- a/riscv/opcodes.h
+++ b/riscv/opcodes.h
@@ -9,6 +9,7 @@ DECLARE_INSN(lb, 0x3, 0x3ff)
 DECLARE_INSN(fcvt_s_wu, 0xf053, 0x3ff1ff)
 DECLARE_INSN(fcvt_d_l, 0xc0d3, 0x3ff1ff)
 DECLARE_INSN(lh, 0x83, 0x3ff)
+DECLARE_INSN(frsr, 0x1d053, 0x7ffffff)
 DECLARE_INSN(fcvt_d_w, 0xe0d3, 0x3ff1ff)
 DECLARE_INSN(lw, 0x103, 0x3ff)
 DECLARE_INSN(add, 0x33, 0x1ffff)
@@ -38,7 +39,6 @@ DECLARE_INSN(fnmsub_s, 0x4b, 0x1ff)
 DECLARE_INSN(fcvt_l_s, 0x8053, 0x3ff1ff)
 DECLARE_INSN(fle_s, 0x17053, 0x1ffff)
 DECLARE_INSN(fence_v_l, 0x22f, 0x3ff)
-DECLARE_INSN(mffsr, 0x1d053, 0x7ffffff)
 DECLARE_INSN(fdiv_s, 0x3053, 0x1f1ff)
 DECLARE_INSN(fle_d, 0x170d3, 0x1ffff)
 DECLARE_INSN(fence_i, 0xaf, 0x3ff)
@@ -49,7 +49,6 @@ DECLARE_INSN(xor, 0x233, 0x1ffff)
 DECLARE_INSN(sub, 0x10033, 0x1ffff)
 DECLARE_INSN(eret, 0x273, 0xffffffff)
 DECLARE_INSN(blt, 0x263, 0x3ff)
-DECLARE_INSN(mtfsr, 0x1f053, 0x3fffff)
 DECLARE_INSN(sc_w, 0x1052b, 0x1ffff)
 DECLARE_INSN(rem, 0x733, 0x1ffff)
 DECLARE_INSN(srliw, 0x29b, 0x3f83ff)
@@ -129,6 +128,7 @@ DECLARE_INSN(amomax_w, 0x152b, 0x1ffff)
 DECLARE_INSN(fsgnj_d, 0x50d3, 0x1ffff)
 DECLARE_INSN(mulhu, 0x5b3, 0x1ffff)
 DECLARE_INSN(fence_v_g, 0x2af, 0x3ff)
+DECLARE_INSN(fssr, 0x1f053, 0x3fffff)
 DECLARE_INSN(setpcr, 0x173, 0x3ff)
 DECLARE_INSN(fcvt_lu_s, 0x9053, 0x3ff1ff)
 DECLARE_INSN(fcvt_s_l, 0xc053, 0x3ff1ff)