[system.ruby.dir_cntrl0]
type=Directory_Controller
-children=directory
+children=directory requestToDir responseFromDir responseFromMemory responseToDir
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
eventq_index=0
number_of_TBEs=256
recycle_latency=10
+requestToDir=system.ruby.dir_cntrl0.requestToDir
+responseFromDir=system.ruby.dir_cntrl0.responseFromDir
+responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory
+responseToDir=system.ruby.dir_cntrl0.responseToDir
ruby_system=system.ruby
system=system
to_mem_ctrl_latency=1
transitions_per_cycle=4
version=0
memory=system.mem_ctrls.port
-requestToDir=system.ruby.network.master[7]
-responseFromDir=system.ruby.network.slave[9]
-responseToDir=system.ruby.network.master[8]
[system.ruby.dir_cntrl0.directory]
type=RubyDirectoryMemory
size=134217728
version=0
+[system.ruby.dir_cntrl0.requestToDir]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[7]
+
+[system.ruby.dir_cntrl0.responseFromDir]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[9]
+
+[system.ruby.dir_cntrl0.responseFromMemory]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+
+[system.ruby.dir_cntrl0.responseToDir]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[8]
+
[system.ruby.dma_cntrl0]
type=DMA_Controller
-children=dma_sequencer
+children=dma_sequencer mandatoryQueue requestToDir responseFromDir
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
dma_sequencer=system.ruby.dma_cntrl0.dma_sequencer
eventq_index=0
+mandatoryQueue=system.ruby.dma_cntrl0.mandatoryQueue
number_of_TBEs=256
recycle_latency=10
+requestToDir=system.ruby.dma_cntrl0.requestToDir
request_latency=6
+responseFromDir=system.ruby.dma_cntrl0.responseFromDir
ruby_system=system.ruby
system=system
transitions_per_cycle=4
version=0
-requestToDir=system.ruby.network.slave[10]
-responseFromDir=system.ruby.network.master[9]
[system.ruby.dma_cntrl0.dma_sequencer]
type=DMASequencer
version=0
slave=system.pc.south_bridge.ide.dma
+[system.ruby.dma_cntrl0.mandatoryQueue]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+
+[system.ruby.dma_cntrl0.requestToDir]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[10]
+
+[system.ruby.dma_cntrl0.responseFromDir]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[9]
+
[system.ruby.io_controller]
type=DMA_Controller
-children=dma_sequencer
+children=dma_sequencer mandatoryQueue requestToDir responseFromDir
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
dma_sequencer=system.ruby.io_controller.dma_sequencer
eventq_index=0
+mandatoryQueue=system.ruby.io_controller.mandatoryQueue
number_of_TBEs=256
recycle_latency=10
+requestToDir=system.ruby.io_controller.requestToDir
request_latency=6
+responseFromDir=system.ruby.io_controller.responseFromDir
ruby_system=system.ruby
system=system
transitions_per_cycle=32
version=1
-requestToDir=system.ruby.network.slave[11]
-responseFromDir=system.ruby.network.master[10]
[system.ruby.io_controller.dma_sequencer]
type=DMASequencer
version=1
slave=system.iobus.master[20]
+[system.ruby.io_controller.mandatoryQueue]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+
+[system.ruby.io_controller.requestToDir]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[11]
+
+[system.ruby.io_controller.responseFromDir]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[10]
+
[system.ruby.l1_cntrl0]
type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
+children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
L1Dcache=system.ruby.l1_cntrl0.L1Dcache
L1Icache=system.ruby.l1_cntrl0.L1Icache
buffer_size=0
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
+mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
number_of_TBEs=256
+optionalQueue=system.ruby.l1_cntrl0.optionalQueue
prefetcher=system.ruby.l1_cntrl0.prefetcher
recycle_latency=10
+requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
+requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
+responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache
+responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache
ruby_system=system.ruby
send_evictions=true
sequencer=system.ruby.l1_cntrl0.sequencer
system=system
to_l2_latency=1
transitions_per_cycle=4
+unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache
version=0
-requestFromL1Cache=system.ruby.network.slave[0]
-requestToL1Cache=system.ruby.network.master[0]
-responseFromL1Cache=system.ruby.network.slave[1]
-responseToL1Cache=system.ruby.network.master[1]
-unblockFromL1Cache=system.ruby.network.slave[2]
[system.ruby.l1_cntrl0.L1Dcache]
type=RubyCache
+children=replacement_policy
assoc=2
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
+replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy
resourceStalls=false
+ruby_system=system.ruby
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
+[system.ruby.l1_cntrl0.L1Dcache.replacement_policy]
+type=PseudoLRUReplacementPolicy
+assoc=2
+block_size=64
+eventq_index=0
+size=32768
+
[system.ruby.l1_cntrl0.L1Icache]
type=RubyCache
+children=replacement_policy
assoc=2
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
+replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy
resourceStalls=false
+ruby_system=system.ruby
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
+[system.ruby.l1_cntrl0.L1Icache.replacement_policy]
+type=PseudoLRUReplacementPolicy
+assoc=2
+block_size=64
+eventq_index=0
+size=32768
+
+[system.ruby.l1_cntrl0.mandatoryQueue]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+
+[system.ruby.l1_cntrl0.optionalQueue]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+
[system.ruby.l1_cntrl0.prefetcher]
type=Prefetcher
cross_page=false
train_misses=4
unit_filter=8
+[system.ruby.l1_cntrl0.requestFromL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[0]
+
+[system.ruby.l1_cntrl0.requestToL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[0]
+
+[system.ruby.l1_cntrl0.responseFromL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[1]
+
+[system.ruby.l1_cntrl0.responseToL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[1]
+
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
+dcache_hit_latency=1
deadlock_threshold=500000
eventq_index=0
icache=system.ruby.l1_cntrl0.L1Icache
+icache_hit_latency=1
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
pio_slave_port=system.iobus.master[18]
slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master
+[system.ruby.l1_cntrl0.unblockFromL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[2]
+
[system.ruby.l1_cntrl1]
type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
+children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache
L1Dcache=system.ruby.l1_cntrl1.L1Dcache
L1Icache=system.ruby.l1_cntrl1.L1Icache
buffer_size=0
l1_request_latency=2
l1_response_latency=2
l2_select_num_bits=0
+mandatoryQueue=system.ruby.l1_cntrl1.mandatoryQueue
number_of_TBEs=256
+optionalQueue=system.ruby.l1_cntrl1.optionalQueue
prefetcher=system.ruby.l1_cntrl1.prefetcher
recycle_latency=10
+requestFromL1Cache=system.ruby.l1_cntrl1.requestFromL1Cache
+requestToL1Cache=system.ruby.l1_cntrl1.requestToL1Cache
+responseFromL1Cache=system.ruby.l1_cntrl1.responseFromL1Cache
+responseToL1Cache=system.ruby.l1_cntrl1.responseToL1Cache
ruby_system=system.ruby
send_evictions=true
sequencer=system.ruby.l1_cntrl1.sequencer
system=system
to_l2_latency=1
transitions_per_cycle=4
+unblockFromL1Cache=system.ruby.l1_cntrl1.unblockFromL1Cache
version=1
-requestFromL1Cache=system.ruby.network.slave[3]
-requestToL1Cache=system.ruby.network.master[2]
-responseFromL1Cache=system.ruby.network.slave[4]
-responseToL1Cache=system.ruby.network.master[3]
-unblockFromL1Cache=system.ruby.network.slave[5]
[system.ruby.l1_cntrl1.L1Dcache]
type=RubyCache
+children=replacement_policy
assoc=2
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
+replacement_policy=system.ruby.l1_cntrl1.L1Dcache.replacement_policy
resourceStalls=false
+ruby_system=system.ruby
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
+[system.ruby.l1_cntrl1.L1Dcache.replacement_policy]
+type=PseudoLRUReplacementPolicy
+assoc=2
+block_size=64
+eventq_index=0
+size=32768
+
[system.ruby.l1_cntrl1.L1Icache]
type=RubyCache
+children=replacement_policy
assoc=2
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
+replacement_policy=system.ruby.l1_cntrl1.L1Icache.replacement_policy
resourceStalls=false
+ruby_system=system.ruby
size=32768
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
+[system.ruby.l1_cntrl1.L1Icache.replacement_policy]
+type=PseudoLRUReplacementPolicy
+assoc=2
+block_size=64
+eventq_index=0
+size=32768
+
+[system.ruby.l1_cntrl1.mandatoryQueue]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+
+[system.ruby.l1_cntrl1.optionalQueue]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+
[system.ruby.l1_cntrl1.prefetcher]
type=Prefetcher
cross_page=false
train_misses=4
unit_filter=8
+[system.ruby.l1_cntrl1.requestFromL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[3]
+
+[system.ruby.l1_cntrl1.requestToL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[2]
+
+[system.ruby.l1_cntrl1.responseFromL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[4]
+
+[system.ruby.l1_cntrl1.responseToL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[3]
+
[system.ruby.l1_cntrl1.sequencer]
type=RubySequencer
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl1.L1Dcache
+dcache_hit_latency=1
deadlock_threshold=500000
eventq_index=0
icache=system.ruby.l1_cntrl1.L1Icache
+icache_hit_latency=1
max_outstanding_requests=16
ruby_system=system.ruby
support_data_reqs=true
pio_slave_port=system.iobus.master[19]
slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master
+[system.ruby.l1_cntrl1.unblockFromL1Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[5]
+
[system.ruby.l2_cntrl0]
type=L2Cache_Controller
-children=L2cache
+children=DirRequestFromL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache unblockToL2Cache
+DirRequestFromL2Cache=system.ruby.l2_cntrl0.DirRequestFromL2Cache
+L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache
+L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache
L2cache=system.ruby.l2_cntrl0.L2cache
buffer_size=0
clk_domain=system.ruby.clk_domain
l2_response_latency=2
number_of_TBEs=256
recycle_latency=10
+responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
+responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
ruby_system=system.ruby
system=system
to_l1_latency=1
transitions_per_cycle=4
+unblockToL2Cache=system.ruby.l2_cntrl0.unblockToL2Cache
version=0
-DirRequestFromL2Cache=system.ruby.network.slave[6]
-L1RequestFromL2Cache=system.ruby.network.slave[7]
-L1RequestToL2Cache=system.ruby.network.master[5]
-responseFromL2Cache=system.ruby.network.slave[8]
-responseToL2Cache=system.ruby.network.master[6]
-unblockToL2Cache=system.ruby.network.master[4]
+
+[system.ruby.l2_cntrl0.DirRequestFromL2Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[6]
+
+[system.ruby.l2_cntrl0.L1RequestFromL2Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[7]
+
+[system.ruby.l2_cntrl0.L1RequestToL2Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[5]
[system.ruby.l2_cntrl0.L2cache]
type=RubyCache
+children=replacement_policy
assoc=2
dataAccessLatency=1
dataArrayBanks=1
eventq_index=0
is_icache=false
-latency=15
-replacement_policy=PSEUDO_LRU
+replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy
resourceStalls=false
+ruby_system=system.ruby
size=4194304
start_index_bit=6
tagAccessLatency=1
tagArrayBanks=1
+[system.ruby.l2_cntrl0.L2cache.replacement_policy]
+type=PseudoLRUReplacementPolicy
+assoc=2
+block_size=64
+eventq_index=0
+size=4194304
+
+[system.ruby.l2_cntrl0.responseFromL2Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+master=system.ruby.network.slave[8]
+
+[system.ruby.l2_cntrl0.responseToL2Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[6]
+
+[system.ruby.l2_cntrl0.unblockToL2Cache]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=false
+randomization=false
+recycle_latency=10
+slave=system.ruby.network.master[4]
+
[system.ruby.memctrl_clk_domain]
type=DerivedClockDomain
clk_divider=3
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 routers4 routers5 routers6
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 int_link_buffers000 int_link_buffers001 int_link_buffers002 int_link_buffers003 int_link_buffers004 int_link_buffers005 int_link_buffers006 int_link_buffers007 int_link_buffers008 int_link_buffers009 int_link_buffers010 int_link_buffers011 int_link_buffers012 int_link_buffers013 int_link_buffers014 int_link_buffers015 int_link_buffers016 int_link_buffers017 int_link_buffers018 int_link_buffers019 int_link_buffers020 int_link_buffers021 int_link_buffers022 int_link_buffers023 int_link_buffers024 int_link_buffers025 int_link_buffers026 int_link_buffers027 int_link_buffers028 int_link_buffers029 int_link_buffers030 int_link_buffers031 int_link_buffers032 int_link_buffers033 int_link_buffers034 int_link_buffers035 int_link_buffers036 int_link_buffers037 int_link_buffers038 int_link_buffers039 int_link_buffers040 int_link_buffers041 int_link_buffers042 int_link_buffers043 int_link_buffers044 int_link_buffers045 int_link_buffers046 int_link_buffers047 int_link_buffers048 int_link_buffers049 int_link_buffers050 int_link_buffers051 int_link_buffers052 int_link_buffers053 int_link_buffers054 int_link_buffers055 int_link_buffers056 int_link_buffers057 int_link_buffers058 int_link_buffers059 int_link_buffers060 int_link_buffers061 int_link_buffers062 int_link_buffers063 int_link_buffers064 int_link_buffers065 int_link_buffers066 int_link_buffers067 int_link_buffers068 int_link_buffers069 int_link_buffers070 int_link_buffers071 int_link_buffers072 int_link_buffers073 int_link_buffers074 int_link_buffers075 int_link_buffers076 int_link_buffers077 int_link_buffers078 int_link_buffers079 int_link_buffers080 int_link_buffers081 int_link_buffers082 int_link_buffers083 int_link_buffers084 int_link_buffers085 int_link_buffers086 int_link_buffers087 int_link_buffers088 int_link_buffers089 int_link_buffers090 int_link_buffers091 int_link_buffers092 int_link_buffers093 int_link_buffers094 int_link_buffers095 int_link_buffers096 int_link_buffers097 int_link_buffers098 int_link_buffers099 int_link_buffers100 int_link_buffers101 int_link_buffers102 int_link_buffers103 int_link_buffers104 int_link_buffers105 int_link_buffers106 int_link_buffers107 int_link_buffers108 int_link_buffers109 int_link_buffers110 int_link_buffers111 int_link_buffers112 int_link_buffers113 int_link_buffers114 int_link_buffers115 int_link_buffers116 int_link_buffers117 int_link_buffers118 int_link_buffers119 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 routers4 routers5 routers6
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5
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int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
netifs=
number_of_virtual_networks=10
+recycle_latency=0
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5 system.ruby.network.routers6
ruby_system=system.ruby
topology=Crossbar
-master=system.ruby.l1_cntrl0.requestToL1Cache system.ruby.l1_cntrl0.responseToL1Cache system.ruby.l1_cntrl1.requestToL1Cache system.ruby.l1_cntrl1.responseToL1Cache system.ruby.l2_cntrl0.unblockToL2Cache system.ruby.l2_cntrl0.L1RequestToL2Cache system.ruby.l2_cntrl0.responseToL2Cache system.ruby.dir_cntrl0.requestToDir system.ruby.dir_cntrl0.responseToDir system.ruby.dma_cntrl0.responseFromDir system.ruby.io_controller.responseFromDir
-slave=system.ruby.l1_cntrl0.requestFromL1Cache system.ruby.l1_cntrl0.responseFromL1Cache system.ruby.l1_cntrl0.unblockFromL1Cache system.ruby.l1_cntrl1.requestFromL1Cache system.ruby.l1_cntrl1.responseFromL1Cache system.ruby.l1_cntrl1.unblockFromL1Cache system.ruby.l2_cntrl0.DirRequestFromL2Cache system.ruby.l2_cntrl0.L1RequestFromL2Cache system.ruby.l2_cntrl0.responseFromL2Cache system.ruby.dir_cntrl0.responseFromDir system.ruby.dma_cntrl0.requestToDir system.ruby.io_controller.requestToDir
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[system.ruby.network.ext_links0]
type=SimpleExtLink
link_id=5
weight=1
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-type=SimpleIntLink
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-node_b=system.ruby.network.routers6
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-[system.ruby.network.int_links3]
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[system.smbios_table]
type=X86SMBiosSMBiosTable
---------- Begin Simulation Statistics ----------
-sim_seconds 5.305855 # Number of seconds simulated
-sim_ticks 5305855051000 # Number of ticks simulated
-final_tick 5305855051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.224199 # Number of seconds simulated
+sim_ticks 5224199387500 # Number of ticks simulated
+final_tick 5224199387500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 191709 # Simulator instruction rate (inst/s)
-host_op_rate 367405 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9489836408 # Simulator tick rate (ticks/s)
-host_mem_usage 1155664 # Number of bytes of host memory used
-host_seconds 559.11 # Real time elapsed on the host
-sim_insts 107186064 # Number of instructions simulated
-sim_ops 205419446 # Number of ops (including micro ops) simulated
+host_inst_rate 181246 # Simulator instruction rate (inst/s)
+host_op_rate 351982 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6214161959 # Simulator tick rate (ticks/s)
+host_mem_usage 1108196 # Number of bytes of host memory used
+host_seconds 840.69 # Real time elapsed on the host
+sim_insts 152372487 # Number of instructions simulated
+sim_ops 295908921 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11371136 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 11371136 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9131456 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 9131456 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 177674 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 177674 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 142679 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 142679 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 2143130 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 2143130 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1721015 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1721015 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 3864145 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 3864145 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 177674 # Number of read requests accepted
-system.mem_ctrls.writeReqs 142679 # Number of write requests accepted
-system.mem_ctrls.readBursts 177674 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 142679 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 11313280 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 57856 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 9121152 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 11371136 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 9131456 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 904 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 135 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 11634048 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 11634048 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 9365120 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 9365120 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 181782 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 181782 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 146330 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 146330 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 2226953 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 2226953 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1792642 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1792642 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 4019595 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 4019595 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 181782 # Number of read requests accepted
+system.mem_ctrls.writeReqs 146330 # Number of write requests accepted
+system.mem_ctrls.readBursts 181782 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 146330 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 11603776 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 30272 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 9361152 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 11634048 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 9365120 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 473 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 34 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 10805 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 10794 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 10981 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 11389 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 11550 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 12175 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 10978 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 10407 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 10706 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 10369 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 10514 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 13718 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 10819 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 10294 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 10714 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 10557 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 8779 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 8773 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 8745 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 9209 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 9395 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 9648 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 8754 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 8594 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 8776 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 8713 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 8651 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 9041 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 8739 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 8605 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 9111 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 8985 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 11150 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 11614 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 11088 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 11198 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 11307 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 11653 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 10979 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 10504 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8 11290 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9 11823 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 12275 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11 12209 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12 11037 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 10843 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 11600 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 10739 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 9147 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 9195 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 8950 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 9212 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 9068 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 9215 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6 8804 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 8265 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8 8949 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9 9397 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 9286 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11 9574 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12 9238 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 9086 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 9706 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15 9176 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 5305854916500 # Total gap between requests
+system.mem_ctrls.totGap 5224199278000 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 177674 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 181782 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
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-system.mem_ctrls.bytesPerActivate::samples 60326 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 338.732354 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 200.613193 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 343.695896 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 20059 33.25% 33.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 14736 24.43% 57.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 6379 10.57% 68.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 3472 5.76% 74.01% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 2656 4.40% 78.41% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 1882 3.12% 81.53% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1369 2.27% 83.80% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1326 2.20% 86.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 8447 14.00% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 60326 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 7898 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 22.379337 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 317.468114 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::0-1023 7892 99.92% 99.92% # Reads before turning the bus around for writes
+system.mem_ctrls.bytesPerActivate::samples 59255 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 353.807510 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 209.383376 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 350.503043 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 19159 32.33% 32.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 13849 23.37% 55.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 6106 10.30% 66.01% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 3747 6.32% 72.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 2604 4.39% 76.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 1953 3.30% 80.02% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 1628 2.75% 82.77% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1375 2.32% 85.09% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 8834 14.91% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 59255 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 8155 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 22.229552 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 312.599698 # Reads before turning the bus around for writes
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system.mem_ctrls.rdPerTurnAround::1024-2047 3 0.04% 99.96% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.97% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::10240-11263 1 0.01% 99.99% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 7898 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 7898 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 18.044821 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.697162 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 4.041167 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 5792 73.34% 73.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 9 0.11% 73.45% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 176 2.23% 75.68% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 20 0.25% 75.93% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 36 0.46% 76.39% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::21 503 6.37% 82.76% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::22 145 1.84% 84.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::23 45 0.57% 85.16% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::24 652 8.26% 93.42% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::25 114 1.44% 94.86% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::26 12 0.15% 95.01% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::27 18 0.23% 95.24% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::28 301 3.81% 99.05% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::29 7 0.09% 99.14% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::30 3 0.04% 99.18% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::31 7 0.09% 99.27% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::32 6 0.08% 99.34% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::33 2 0.03% 99.37% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.38% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::35 3 0.04% 99.42% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::37 1 0.01% 99.43% # Writes before turning the bus around for reads
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-system.mem_ctrls.wrPerTurnAround::39 7 0.09% 99.56% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::40 3 0.04% 99.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.63% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::42 6 0.08% 99.71% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::43 2 0.03% 99.73% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::44 7 0.09% 99.82% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::45 1 0.01% 99.84% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::47 1 0.01% 99.85% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::48 4 0.05% 99.90% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::51 7 0.09% 99.99% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::52 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 7898 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 1934412994 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 5248850494 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 883850000 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 10943.11 # Average queueing delay per DRAM burst
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+system.mem_ctrls.wrPerTurnAround::22 184 2.26% 85.63% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::23 46 0.56% 86.19% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::24 633 7.76% 93.95% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::25 108 1.32% 95.28% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::26 7 0.09% 95.36% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::27 19 0.23% 95.60% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::28 284 3.48% 99.08% # Writes before turning the bus around for reads
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+system.mem_ctrls.wrPerTurnAround::34 1 0.01% 99.46% # Writes before turning the bus around for reads
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+system.mem_ctrls.wrPerTurnAround::37 4 0.05% 99.58% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::38 3 0.04% 99.62% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::39 6 0.07% 99.69% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::40 4 0.05% 99.74% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::41 3 0.04% 99.78% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::43 3 0.04% 99.82% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::44 5 0.06% 99.88% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::45 2 0.02% 99.90% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::46 3 0.04% 99.94% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::48 2 0.02% 99.96% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::51 3 0.04% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 8155 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 1909551997 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 5309095747 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 906545000 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 10532.03 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 29693.11 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 2.13 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 1.72 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 2.14 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1.72 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 29282.03 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 1.79 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 2.23 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1.79 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 0.03 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 24.42 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 140781 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 118180 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 79.64 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 82.91 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 16562526.08 # Average gap between requests
-system.mem_ctrls.pageHitRate 81.10 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 229725720 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 125346375 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 694816200 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 465892560 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 149158105020 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 3052672353000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 3549898856715 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 669.053166 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 5078226654500 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 177174140000 # Time in different power states
+system.mem_ctrls.avgWrQLen 24.22 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 147266 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 121055 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 81.22 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 82.75 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 15922000.04 # Average gap between requests
+system.mem_ctrls.pageHitRate 81.90 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 216465480 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 118111125 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 698037600 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 465626880 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 341218840560 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 139333087125 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 3012293484000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 3494343652770 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 668.877279 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 5011116201500 # Time in different power states
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system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 50453879250 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 38635825500 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 226338840 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 123498375 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 683982000 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 457624080 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 346552617840 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 148581064665 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3053178528750 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 3549803654550 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 669.035223 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5079073326250 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 177174140000 # Time in different power states
+system.mem_ctrls_1.actEnergy 231502320 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 126315750 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 716164800 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 482189760 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 341218840560 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 140605884585 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 3011176995000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 3494557892775 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 668.918288 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5009239707000 # Time in different power states
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system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 49607460250 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 40505530500 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu0.numCycles 10611710102 # number of cpu cycles simulated
+system.cpu0.numCycles 10448398775 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 59039301 # Number of instructions committed
-system.cpu0.committedOps 113305603 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 106292175 # Number of integer alu accesses
+system.cpu0.committedInsts 134854206 # Number of instructions committed
+system.cpu0.committedOps 263157336 # Number of ops (including micro ops) committed
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system.cpu0.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu0.num_func_calls 1017385 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 10037487 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 106292175 # number of integer instructions
+system.cpu0.num_func_calls 2136969 # number of times a function call or return occured
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system.cpu0.num_fp_insts 48 # number of float instructions
-system.cpu0.num_int_register_reads 200616462 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 90211252 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 453367941 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 210194907 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 60966419 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 44030869 # number of times the CC registers were written
-system.cpu0.num_mem_refs 12456032 # number of memory refs
-system.cpu0.num_load_insts 7518229 # Number of load instructions
-system.cpu0.num_store_insts 4937803 # Number of store instructions
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-system.cpu0.not_idle_fraction 0.049291 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.950709 # Percentage of idle cycles
-system.cpu0.Branches 11416956 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 131098 0.12% 0.12% # Class of executed instruction
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-system.cpu0.op_class::total 113306520 # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu1.numCycles 10608777066 # number of cpu cycles simulated
+system.cpu1.numCycles 10447240338 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 48146763 # Number of instructions committed
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-system.cpu1.num_int_alu_accesses 88441904 # Number of integer alu accesses
+system.cpu1.committedInsts 17518281 # Number of instructions committed
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system.cpu1.num_fp_alu_accesses 48 # Number of float alu accesses
-system.cpu1.num_func_calls 1752446 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 8219762 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 88441904 # number of integer instructions
+system.cpu1.num_func_calls 684497 # number of times a function call or return occured
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system.cpu1.num_fp_insts 48 # number of float instructions
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-system.cpu1.num_int_register_writes 73196146 # number of times the integer registers were written
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system.cpu1.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 50924744 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 32745968 # number of times the CC registers were written
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-system.cpu1.not_idle_fraction 0.031550 # Percentage of non-idle cycles
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-system.cpu1.op_class::No_OpClass 169787 0.18% 0.18% # Class of executed instruction
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+system.cpu1.not_idle_fraction 0.007816 # Percentage of non-idle cycles
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+system.cpu1.op_class::No_OpClass 121362 0.37% 0.37% # Class of executed instruction
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system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.iobus.trans_dist::ReadReq 842290 # Transaction distribution
-system.iobus.trans_dist::ReadResp 842290 # Transaction distribution
-system.iobus.trans_dist::WriteReq 35657 # Transaction distribution
-system.iobus.trans_dist::WriteResp 35657 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1791 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1791 # Transaction distribution
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5758 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 968 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 66 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 907253 # Transaction distribution
+system.iobus.trans_dist::ReadResp 907253 # Transaction distribution
+system.iobus.trans_dist::WriteReq 37589 # Transaction distribution
+system.iobus.trans_dist::WriteResp 37589 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1832 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1832 # Transaction distribution
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1742 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1688 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3430 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 52 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6724 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 960 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 46 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 917434 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 964 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 90 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 943400 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1332 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 178 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14814 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 729402 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 158 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 21174 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 831240 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1671974 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5284 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 396 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 28 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30330 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 384 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 30418 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12448 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4614 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 84154 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 1759476 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3266 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 484 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 33 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1807744 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4456 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 404 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 32826 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 788 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 32826 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6198 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 64 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 4596 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 82174 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 1893348 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3484 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3376 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6860 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 26 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4231 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 480 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 23 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 458717 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1928 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 45 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 471700 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 2664 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 89 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7407 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1458798 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 316 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 10587 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1662474 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 340 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1935448 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3394 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 198 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 14 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15165 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 768 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 15209 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6224 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9225 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 50463 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 1992607 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 2157168 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2507 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 202 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 4 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16413 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1576 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist1.pio 16413 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 3099 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 128 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 9189 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 49535 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2213563 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 43500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 9032000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 9190500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 154500 # Layer occupancy (ticks)
+system.iobus.reqLayer3.occupancy 158000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 52500 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 30508000 # Layer occupancy (ticks)
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system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
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system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
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system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions.
system.ruby.clk_domain.clock 500 # Clock period in ticks
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
-system.ruby.delayHist::samples 10891037 # delay histogram for all message
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-system.ruby.delayHist | 10288749 94.47% 94.47% | 1200 0.01% 94.48% | 600645 5.52% 100.00% | 149 0.00% 100.00% | 250 0.00% 100.00% | 10 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
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+system.ruby.delayHist::total 11129562 # delay histogram for all message
system.ruby.outstanding_req_hist::bucket_size 1
system.ruby.outstanding_req_hist::max_bucket 9
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-system.ruby.outstanding_req_hist::gmean 1.000115
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system.ruby.hit_latency_hist::bucket_size 1
system.ruby.hit_latency_hist::max_bucket 9
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system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
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system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
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system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks
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system.ruby.network.routers6.throttle4.msg_count.Writeback_Control::1 46736
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system.ruby.network.routers6.throttle4.msg_bytes.Writeback_Control::1 373888
system.ruby.network.routers6.throttle5.link_utilization 0
system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 6109490 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 0.754288 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 2.340197 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 5534078 90.58% 90.58% | 346 0.01% 90.59% | 574634 9.41% 99.99% | 147 0.00% 100.00% | 241 0.00% 100.00% | 10 0.00% 100.00% | 34 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 6109490 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples 6209515 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean 0.707046 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 2.283958 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 5663572 91.21% 91.21% | 1821 0.03% 91.24% | 541762 8.72% 99.96% | 478 0.01% 99.97% | 1759 0.03% 100.00% | 21 0.00% 100.00% | 100 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 6209515 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 4698350 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.045551 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.599594 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 4670978 99.42% 99.42% | 496 0.01% 99.43% | 327 0.01% 99.43% | 527 0.01% 99.45% | 25863 0.55% 100.00% | 148 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% | 9 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 4698350 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 4787110 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean 0.088019 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 0.824587 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 4731394 98.84% 98.84% | 1825 0.04% 98.87% | 2296 0.05% 98.92% | 2690 0.06% 98.98% | 48377 1.01% 99.99% | 509 0.01% 100.00% | 7 0.00% 100.00% | 0 0.00% 100.00% | 11 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 4787110 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 83197 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::mean 0.000144 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::stdev 0.016984 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 83191 99.99% 99.99% | 0 0.00% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 83197 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 132937 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::mean 0.000451 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::stdev 0.030041 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 132907 99.98% 99.98% | 0 0.00% 99.98% | 30 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
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system.ruby.LD.latency_hist::bucket_size 128
system.ruby.LD.latency_hist::max_bucket 1279
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-system.ruby.LD.latency_hist::mean 4.869031
-system.ruby.LD.latency_hist::gmean 3.591146
-system.ruby.LD.latency_hist::stdev 9.232635
-system.ruby.LD.latency_hist | 15011953 99.89% 99.89% | 13856 0.09% 99.99% | 858 0.01% 99.99% | 788 0.01% 100.00% | 329 0.00% 100.00% | 120 0.00% 100.00% | 2 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.LD.latency_hist::total 15027915
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+system.ruby.LD.latency_hist::gmean 1.304177
+system.ruby.LD.latency_hist::stdev 8.972746
+system.ruby.LD.latency_hist | 15777332 99.91% 99.91% | 12811 0.08% 99.99% | 834 0.01% 99.99% | 747 0.00% 100.00% | 344 0.00% 100.00% | 100 0.00% 100.00% | 3 0.00% 100.00% | 8 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.hit_latency_hist::bucket_size 1
system.ruby.LD.hit_latency_hist::max_bucket 9
-system.ruby.LD.hit_latency_hist::samples 13637262
-system.ruby.LD.hit_latency_hist::mean 3
-system.ruby.LD.hit_latency_hist::gmean 3.000000
-system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13637262 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist::total 13637262
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+system.ruby.LD.hit_latency_hist::mean 1
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+system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 14362699 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.LD.miss_latency_hist::bucket_size 128
system.ruby.LD.miss_latency_hist::max_bucket 1279
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-system.ruby.LD.miss_latency_hist::gmean 20.952063
-system.ruby.LD.miss_latency_hist::stdev 23.472645
-system.ruby.LD.miss_latency_hist | 1374691 98.85% 98.85% | 13856 1.00% 99.85% | 858 0.06% 99.91% | 788 0.06% 99.97% | 329 0.02% 99.99% | 120 0.01% 100.00% | 2 0.00% 100.00% | 4 0.00% 100.00% | 4 0.00% 100.00% | 1 0.00% 100.00%
-system.ruby.LD.miss_latency_hist::total 1390653
-system.ruby.ST.latency_hist::bucket_size 128
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-system.ruby.ST.latency_hist::gmean 3.300097
-system.ruby.ST.latency_hist::stdev 17.574774
-system.ruby.ST.latency_hist | 9544786 99.85% 99.85% | 8165 0.09% 99.94% | 1340 0.01% 99.95% | 2484 0.03% 99.98% | 1636 0.02% 100.00% | 338 0.00% 100.00% | 8 0.00% 100.00% | 10 0.00% 100.00% | 10 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.ST.latency_hist::total 9558783
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+system.ruby.LD.miss_latency_hist::gmean 18.800854
+system.ruby.LD.miss_latency_hist::stdev 22.913162
+system.ruby.LD.miss_latency_hist | 1414633 98.96% 98.96% | 12811 0.90% 99.86% | 834 0.06% 99.92% | 747 0.05% 99.97% | 344 0.02% 99.99% | 100 0.01% 100.00% | 3 0.00% 100.00% | 8 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.ST.latency_hist::stdev 17.669492
+system.ruby.ST.latency_hist | 9814336 99.94% 99.94% | 3870 0.04% 99.98% | 1895 0.02% 100.00% | 27 0.00% 100.00% | 19 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.ST.hit_latency_hist::bucket_size 1
system.ruby.ST.hit_latency_hist::max_bucket 9
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-system.ruby.ST.hit_latency_hist::mean 3
-system.ruby.ST.hit_latency_hist::gmean 3.000000
-system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9207752 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.ST.miss_latency_hist::stdev 71.047969
-system.ruby.ST.miss_latency_hist | 337034 96.01% 96.01% | 8165 2.33% 98.34% | 1340 0.38% 98.72% | 2484 0.71% 99.43% | 1636 0.47% 99.89% | 338 0.10% 99.99% | 8 0.00% 99.99% | 10 0.00% 100.00% | 10 0.00% 100.00% | 6 0.00% 100.00%
-system.ruby.ST.miss_latency_hist::total 351031
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+system.ruby.ST.miss_latency_hist | 346031 98.35% 98.35% | 3870 1.10% 99.45% | 1895 0.54% 99.99% | 27 0.01% 99.99% | 19 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.IFETCH.latency_hist::bucket_size 128
system.ruby.IFETCH.latency_hist::max_bucket 1279
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-system.ruby.IFETCH.latency_hist::stdev 2.235323
-system.ruby.IFETCH.latency_hist | 126989653 99.99% 99.99% | 5672 0.00% 100.00% | 481 0.00% 100.00% | 320 0.00% 100.00% | 141 0.00% 100.00% | 54 0.00% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.IFETCH.latency_hist | 173516994 100.00% 100.00% | 5126 0.00% 100.00% | 502 0.00% 100.00% | 299 0.00% 100.00% | 121 0.00% 100.00% | 47 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.IFETCH.hit_latency_hist::bucket_size 1
system.ruby.IFETCH.hit_latency_hist::max_bucket 9
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-system.ruby.IFETCH.hit_latency_hist::mean 3
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-system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 126180143 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.IFETCH.hit_latency_hist::mean 1
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system.ruby.IFETCH.miss_latency_hist::bucket_size 128
system.ruby.IFETCH.miss_latency_hist::max_bucket 1279
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-system.ruby.IFETCH.miss_latency_hist | 809510 99.18% 99.18% | 5672 0.69% 99.88% | 481 0.06% 99.94% | 320 0.04% 99.98% | 141 0.02% 99.99% | 54 0.01% 100.00% | 0 0.00% 100.00% | 5 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00%
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+system.ruby.IFETCH.miss_latency_hist | 780506 99.23% 99.23% | 5126 0.65% 99.88% | 502 0.06% 99.94% | 299 0.04% 99.98% | 121 0.02% 99.99% | 47 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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system.ruby.RMW_Read.latency_hist::bucket_size 128
system.ruby.RMW_Read.latency_hist::max_bucket 1279
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-system.ruby.RMW_Read.latency_hist::gmean 3.952377
-system.ruby.RMW_Read.latency_hist::stdev 10.350675
-system.ruby.RMW_Read.latency_hist | 494091 99.96% 99.96% | 129 0.03% 99.99% | 18 0.00% 99.99% | 18 0.00% 100.00% | 12 0.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
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-system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23529
-system.ruby.L1Cache_Controller.M.Fwd_GETS | 13255 56.66% 56.66% | 10137 43.34% 100.00%
-system.ruby.L1Cache_Controller.M.Fwd_GETS::total 23392
+system.ruby.L1Cache_Controller.Data | 1761 60.45% 60.45% | 1152 39.55% 100.00%
+system.ruby.L1Cache_Controller.Data::total 2913
+system.ruby.L1Cache_Controller.Data_Exclusive | 1215318 92.51% 92.51% | 98439 7.49% 100.00%
+system.ruby.L1Cache_Controller.Data_Exclusive::total 1313757
+system.ruby.L1Cache_Controller.DataS_fromL1 | 23095 49.36% 49.36% | 23691 50.64% 100.00%
+system.ruby.L1Cache_Controller.DataS_fromL1::total 46786
+system.ruby.L1Cache_Controller.Data_all_Acks | 847898 66.44% 66.44% | 428223 33.56% 100.00%
+system.ruby.L1Cache_Controller.Data_all_Acks::total 1276121
+system.ruby.L1Cache_Controller.Ack | 20479 48.23% 48.23% | 21984 51.77% 100.00%
+system.ruby.L1Cache_Controller.Ack::total 42463
+system.ruby.L1Cache_Controller.Ack_all | 22240 49.01% 49.01% | 23136 50.99% 100.00%
+system.ruby.L1Cache_Controller.Ack_all::total 45376
+system.ruby.L1Cache_Controller.WB_Ack | 1499568 88.16% 88.16% | 201409 11.84% 100.00%
+system.ruby.L1Cache_Controller.WB_Ack::total 1700977
+system.ruby.L1Cache_Controller.NP.Load | 1266490 90.67% 90.67% | 130317 9.33% 100.00%
+system.ruby.L1Cache_Controller.NP.Load::total 1396807
+system.ruby.L1Cache_Controller.NP.Ifetch | 501126 63.78% 63.78% | 284584 36.22% 100.00%
+system.ruby.L1Cache_Controller.NP.Ifetch::total 785710
+system.ruby.L1Cache_Controller.NP.Store | 296269 72.69% 72.69% | 111321 27.31% 100.00%
+system.ruby.L1Cache_Controller.NP.Store::total 407590
+system.ruby.L1Cache_Controller.NP.Inv | 6842 68.45% 68.45% | 3153 31.55% 100.00%
+system.ruby.L1Cache_Controller.NP.Inv::total 9995
+system.ruby.L1Cache_Controller.I.Load | 16433 50.29% 50.29% | 16243 49.71% 100.00%
+system.ruby.L1Cache_Controller.I.Load::total 32676
+system.ruby.L1Cache_Controller.I.Ifetch | 448 50.22% 50.22% | 444 49.78% 100.00%
+system.ruby.L1Cache_Controller.I.Ifetch::total 892
+system.ruby.L1Cache_Controller.I.Store | 7300 45.93% 45.93% | 8594 54.07% 100.00%
+system.ruby.L1Cache_Controller.I.Store::total 15894
+system.ruby.L1Cache_Controller.I.L1_Replacement | 14321 53.77% 53.77% | 12311 46.23% 100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total 26632
+system.ruby.L1Cache_Controller.S.Load | 961054 62.74% 62.74% | 570843 37.26% 100.00%
+system.ruby.L1Cache_Controller.S.Load::total 1531897
+system.ruby.L1Cache_Controller.S.Ifetch | 150537966 87.15% 87.15% | 22198522 12.85% 100.00%
+system.ruby.L1Cache_Controller.S.Ifetch::total 172736488
+system.ruby.L1Cache_Controller.S.Store | 20485 48.23% 48.23% | 21986 51.77% 100.00%
+system.ruby.L1Cache_Controller.S.Store::total 42471
+system.ruby.L1Cache_Controller.S.Inv | 22871 50.77% 50.77% | 22179 49.23% 100.00%
+system.ruby.L1Cache_Controller.S.Inv::total 45050
+system.ruby.L1Cache_Controller.S.L1_Replacement | 548974 63.80% 63.80% | 311478 36.20% 100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total 860452
+system.ruby.L1Cache_Controller.E.Load | 3041832 82.22% 82.22% | 657704 17.78% 100.00%
+system.ruby.L1Cache_Controller.E.Load::total 3699536
+system.ruby.L1Cache_Controller.E.Store | 119741 78.96% 78.96% | 31903 21.04% 100.00%
+system.ruby.L1Cache_Controller.E.Store::total 151644
+system.ruby.L1Cache_Controller.E.Inv | 35 14.46% 14.46% | 207 85.54% 100.00%
+system.ruby.L1Cache_Controller.E.Inv::total 242
+system.ruby.L1Cache_Controller.E.L1_Replacement | 1093821 94.41% 94.41% | 64765 5.59% 100.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement::total 1158586
+system.ruby.L1Cache_Controller.E.Fwd_GETX | 218 66.87% 66.87% | 108 33.13% 100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETX::total 326
+system.ruby.L1Cache_Controller.E.Fwd_GETS | 1319 49.83% 49.83% | 1328 50.17% 100.00%
+system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2647
+system.ruby.L1Cache_Controller.M.Load | 6442495 70.55% 70.55% | 2688771 29.45% 100.00%
+system.ruby.L1Cache_Controller.M.Load::total 9131266
+system.ruby.L1Cache_Controller.M.Store | 7279359 69.89% 69.89% | 3136609 30.11% 100.00%
+system.ruby.L1Cache_Controller.M.Store::total 10415968
+system.ruby.L1Cache_Controller.M.Inv | 218 32.68% 32.68% | 449 67.32% 100.00%
+system.ruby.L1Cache_Controller.M.Inv::total 667
+system.ruby.L1Cache_Controller.M.L1_Replacement | 405747 74.81% 74.81% | 136644 25.19% 100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total 542391
+system.ruby.L1Cache_Controller.M.Fwd_GETX | 15164 50.78% 50.78% | 14699 49.22% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total 29863
+system.ruby.L1Cache_Controller.M.Fwd_GETS | 22368 50.68% 50.68% | 21767 49.32% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total 44135
system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4
-system.ruby.L1Cache_Controller.IS.Data_Exclusive | 252714 19.73% 19.73% | 1028028 80.27% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1280742
-system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 11346 44.32% 44.32% | 14255 55.68% 100.00%
-system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25601
-system.ruby.L1Cache_Controller.IS.Data_all_Acks | 348968 38.75% 38.75% | 551527 61.25% 100.00%
-system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 900495
-system.ruby.L1Cache_Controller.IM.Data | 818 44.46% 44.46% | 1022 55.54% 100.00%
-system.ruby.L1Cache_Controller.IM.Data::total 1840
-system.ruby.L1Cache_Controller.IM.Data_all_Acks | 230353 53.43% 53.43% | 200780 46.57% 100.00%
-system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 431133
-system.ruby.L1Cache_Controller.SM.Ack | 12225 54.44% 54.44% | 10230 45.56% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack::total 22455
-system.ruby.L1Cache_Controller.SM.Ack_all | 13043 53.69% 53.69% | 11252 46.31% 100.00%
-system.ruby.L1Cache_Controller.SM.Ack_all::total 24295
-system.ruby.L1Cache_Controller.M_I.Ifetch | 5 83.33% 83.33% | 1 16.67% 100.00%
-system.ruby.L1Cache_Controller.M_I.Ifetch::total 6
-system.ruby.L1Cache_Controller.M_I.WB_Ack | 468895 27.82% 27.82% | 1216558 72.18% 100.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1685453
-system.ruby.L2Cache_Controller.L1_GET_INSTR 816185 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 1390825 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETX 432975 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_UPGRADE 22455 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 1685453 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 95536 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 15120 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 177212 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 112431 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data 23764 0.00% 0.00%
-system.ruby.L2Cache_Controller.WB_Data_clean 2205 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack 1487 0.00% 0.00%
-system.ruby.L2Cache_Controller.Ack_all 7462 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 25601 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 1736170 0.00% 0.00%
-system.ruby.L2Cache_Controller.MEM_Inv 3550 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 16316 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 33914 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETX 126982 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 799839 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETS 84314 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_GETX 1944 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22455 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement 252 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7120 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive | 1215318 92.51% 92.51% | 98439 7.49% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1313757
+system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 23095 49.36% 49.36% | 23691 50.64% 100.00%
+system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 46786
+system.ruby.L1Cache_Controller.IS.Data_all_Acks | 546084 63.83% 63.83% | 309458 36.17% 100.00%
+system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 855542
+system.ruby.L1Cache_Controller.IM.Data | 1761 60.45% 60.45% | 1152 39.55% 100.00%
+system.ruby.L1Cache_Controller.IM.Data::total 2913
+system.ruby.L1Cache_Controller.IM.Data_all_Acks | 301814 71.76% 71.76% | 118765 28.24% 100.00%
+system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 420579
+system.ruby.L1Cache_Controller.SM.Inv | 6 75.00% 75.00% | 2 25.00% 100.00%
+system.ruby.L1Cache_Controller.SM.Inv::total 8
+system.ruby.L1Cache_Controller.SM.Ack | 20479 48.23% 48.23% | 21984 51.77% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total 42463
+system.ruby.L1Cache_Controller.SM.Ack_all | 22240 49.01% 49.01% | 23136 50.99% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack_all::total 45376
+system.ruby.L1Cache_Controller.M_I.Ifetch | 4 80.00% 80.00% | 1 20.00% 100.00%
+system.ruby.L1Cache_Controller.M_I.Ifetch::total 5
+system.ruby.L1Cache_Controller.M_I.WB_Ack | 1499568 88.16% 88.16% | 201409 11.84% 100.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1700977
+system.ruby.L2Cache_Controller.L1_GET_INSTR 786602 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 1429851 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 423493 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_UPGRADE 42471 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 1700977 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 99083 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 14933 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 181331 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 117015 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data 44806 0.00% 0.00%
+system.ruby.L2Cache_Controller.WB_Data_clean 2647 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack 2257 0.00% 0.00%
+system.ruby.L2Cache_Controller.Ack_all 7662 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 46786 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 1779712 0.00% 0.00%
+system.ruby.L2Cache_Controller.MEM_Inv 5998 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15983 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 33150 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 132198 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 770589 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS 68944 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETX 3072 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_UPGRADE 42463 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement 229 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 7185 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.MEM_Inv 6 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GET_INSTR 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETS 1246828 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L1_GETX 280063 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 95163 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7896 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.MEM_Inv 1542 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 1280607 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 258033 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 98530 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 7402 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.MEM_Inv 2754 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETS 25597 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_GETX 23984 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 1685453 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement 121 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 104 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.MEM_Inv 230 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 112431 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.MEM_Inv 1542 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.WB_Data 308 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.Ack_all 43 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_I.MEM_Inv 230 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00%
-system.ruby.L2Cache_Controller.MCT_I.Ack_all 44 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack 1232 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_I.Ack_all 7120 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack 255 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.Ack_all 255 0.00% 0.00%
-system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 33914 0.00% 0.00%
-system.ruby.L2Cache_Controller.IS.Mem_Data 16316 0.00% 0.00%
-system.ruby.L2Cache_Controller.IM.Mem_Data 126982 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.L1_GETS 124 0.00% 0.00%
-system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 24399 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETS 48 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.L1_GETX 2 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1711771 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data 23386 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2205 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IIB.Unblock 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_IB.WB_Data 10 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_SB.Unblock 25591 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETS 46782 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_GETX 30189 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 1700977 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement 324 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 346 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.MEM_Inv 239 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 117015 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.MEM_Inv 2754 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.WB_Data 515 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.Ack_all 48 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_I.MEM_Inv 239 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.WB_Data 152 0.00% 0.00%
+system.ruby.L2Cache_Controller.MCT_I.Ack_all 194 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack 2023 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_I.Ack_all 7185 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack 234 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.Ack_all 235 0.00% 0.00%
+system.ruby.L2Cache_Controller.S_I.MEM_Inv 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 33150 0.00% 0.00%
+system.ruby.L2Cache_Controller.IS.Mem_Data 15983 0.00% 0.00%
+system.ruby.L2Cache_Controller.IM.Mem_Data 132198 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_GETS 234 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.L1_UPGRADE 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 45535 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETS 134 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1734177 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data 44127 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2647 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IIB.Unblock 12 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_IB.WB_Data 12 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_SB.Unblock 46774 0.00% 0.00%
---------- End Simulation Statistics ----------