|| (VALUE) == CONST0_RTX (SFmode)) \
: 0)
+/* Optional extra constraints for this machine.
+
+ For the VAX, `Q' means that OP is a MEM that does not have a mode-dependent
+ address. */
+
+#define EXTRA_CONSTRAINT(OP, C) \
+ ((C) == 'Q' \
+ ? GET_CODE (OP) == MEM && ! mode_dependent_address_p (XEXP (OP, 0)) \
+ : 0)
+
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
"j%C0 %l1") ; %C0 negates condition
\f
;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
-;; if this insn is SImode in the hardware. However, if it is memory,
-;; we use QImode. So we can't allow the memory address to be indexed.
+;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
+;; memory, we use QImode in the insn. So we can't use those instructions
+;; for mode-dependent addresses.
(define_insn ""
[(set (pc)
(if_then_else
- (ne (zero_extract:SI (match_operand:QI 0 "reg_or_nxmem_operand" "g,g")
+ (ne (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
(const_int 1)
(match_operand:SI 1 "general_operand" "I,g"))
(const_int 0))
(define_insn ""
[(set (pc)
(if_then_else
- (eq (zero_extract:SI (match_operand:QI 0 "reg_or_nxmem_operand" "g,g")
+ (eq (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rQ,g")
(const_int 1)
(match_operand:SI 1 "general_operand" "I,g"))
(const_int 0))