xilinx: Add correct signed behaviour to DSP48E1 model

Signed-off-by: David Shah <dave@ds0.me>

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 99120452c6e2304d8f0c3d68e57dc526dc6ef40e..ea5a3b788b89256ed46fcd9fe3105f043d4d1d0d 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -506,6 +506,6 @@ module DSP48E1 (
         if (PCIN != 48'b0)          $fatal(1, "Unsupported PCIN value");
         if (CARRYIN != 1'b0)        $fatal(1, "Unsupported CARRYIN value");
 `endif
-        P[42:0] <= A[24:0] * B;
+        P[42:0] <= $signed(A[24:0]) * $signed(B);
     end
 endmodule