arch-arm: Stop "using namespace std"

Change-Id: If0f373bdaadce81c5ebbc37b03810335c42dd10a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39561
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index 1ce9705e66a0f42f459424a3e3d1ec4f8d4f40cd..e20aef941820775423f342d3f8356a8ff1837b52 100644 (file)
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -45,7 +45,6 @@
 #include "arch/arm/generated/decoder.hh"
 #include "arch/arm/insts/neon64_mem.hh"
 
-using namespace std;
 using namespace ArmISAInst;
 
 namespace ArmISA

diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index e44fc9614de99a0bc9d99d5627e0d2c5d46f3554..8ee3f4929058e6df609b8d937906279706963471 100644 (file)
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -42,8 +42,6 @@
 
 #include "base/loader/symtab.hh"
 
-using namespace std;
-
 namespace ArmISA
 {
 
@@ -75,10 +73,10 @@ MemoryReg::printOffset(std::ostream &os) const
     }
 }
 
-string
+std::string
 RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
-    stringstream ss;
+    std::stringstream ss;
     switch (mode) {
       case DecrementAfter:
         printMnemonic(ss, "da");
@@ -100,10 +98,10 @@ RfeOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
     return ss.str();
 }
 
-string
+std::string
 SrsOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
 {
-    stringstream ss;
+    std::stringstream ss;
     switch (mode) {
       case DecrementAfter:
         printMnemonic(ss, "da");

diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index ed159becaf582181c13be92518f77cfe4861a1ef..44fe7357bfcf71960998df397f03ee712be5f745 100644 (file)
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -41,8 +41,6 @@
 #include "base/loader/symtab.hh"
 #include "mem/request.hh"
 
-using namespace std;
-
 namespace ArmISA
 {
 

diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index 7f86c24fe3a5eda3d16c025f35b1ee9a5bc48f22..cba3d147ace426d46328cb54a61e4970ce9d740c 100644 (file)
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -54,7 +54,6 @@
 #include "sim/syscall_emul.hh"
 #include "sim/system.hh"
 
-using namespace std;
 using namespace ArmISA;
 
 const Addr ArmLinuxProcess32::commPage = 0xffff0000;

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index b5af9b659eb63aad2e5e5b5c871648ea3b3b9c38..5dfbd48274d985bd5fd3a541b166aa44523583f5 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -333,8 +333,6 @@ decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
     return MISCREG_CP14_UNIMPL;
 }
 
-using namespace std;
-
 MiscRegIndex
 decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
 {
@@ -3393,7 +3391,7 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
     return MISCREG_UNKNOWN;
 }
 
-bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
+std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS]; // initialized below
 
 void
 ISA::initializeMiscRegMetadata()

diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 7424eb3c9d422ee62b8287a91b36e9aa295ac35c..aa9338417e3ba25cede7e0b57e8b81d9e4025fcb 100644 (file)
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -41,7 +41,6 @@
 #include "base/bitfield.hh"
 
 using namespace ArmISA;
-using namespace std;
 
 bool
 ArmISA::calculateTBI(ThreadContext* tc, ExceptionLevel el,
@@ -101,11 +100,11 @@ ArmISA::calculateBottomPACBit(ThreadContext* tc, ExceptionLevel el,
         using64k  = el == EL2 ? tcr2.tg0 == 0x1 : tcr3.tg0 == 0x1 ;
     }
     uint32_t max_limit_tsz_field = using64k ? 47 : 48;
-    tsz_field = min(tsz_field, max_limit_tsz_field);
+    tsz_field = std::min(tsz_field, max_limit_tsz_field);
     const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
 
     uint32_t tszmin = (using64k && (bool)mm_fr2.varange) ? 12 : 16;
-    tsz_field = max(tsz_field, tszmin);
+    tsz_field = std::max(tsz_field, tszmin);
 
     return (64-tsz_field);
 }

diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 6f37d1196ea21fc6d35b62419bed7b5d5e100953..86bc8e21129e8a679b85033e1d9043c7d4252607 100644 (file)
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -55,7 +55,6 @@
 #include "sim/syscall_return.hh"
 #include "sim/system.hh"
 
-using namespace std;
 using namespace ArmISA;
 
 ArmProcess::ArmProcess(const ProcessParams &params,
@@ -78,9 +77,9 @@ ArmProcess32::ArmProcess32(const ProcessParams &params,
     Addr next_thread_stack_base = stack_base - max_stack_size;
     Addr mmap_end = 0x40000000L;
 
-    memState = make_shared<MemState>(this, brk_point, stack_base,
-                                     max_stack_size, next_thread_stack_base,
-                                     mmap_end);
+    memState = std::make_shared<MemState>(
+            this, brk_point, stack_base, max_stack_size,
+            next_thread_stack_base, mmap_end);
 }
 
 ArmProcess64::ArmProcess64(
@@ -94,9 +93,9 @@ ArmProcess64::ArmProcess64(
     Addr next_thread_stack_base = stack_base - max_stack_size;
     Addr mmap_end = 0x4000000000L;
 
-    memState = make_shared<MemState>(this, brk_point, stack_base,
-                                     max_stack_size, next_thread_stack_base,
-                                     mmap_end);
+    memState = std::make_shared<MemState>(
+            this, brk_point, stack_base, max_stack_size,
+            next_thread_stack_base, mmap_end);
 }
 
 void
@@ -257,7 +256,7 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
 
     std::vector<AuxVector<IntType>> auxv;
 
-    string filename;
+    std::string filename;
     if (argv.size() < 1)
         filename = "";
     else
@@ -318,7 +317,7 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
     // A sentry NULL void pointer at the top of the stack.
     int sentry_size = intSize;
 
-    string platform = "v71";
+    std::string platform = "v71";
     int platform_size = platform.size() + 1;
 
     // Bytes for AT_RANDOM above, we'll just keep them 0

diff --git a/src/arch/arm/qarma.cc b/src/arch/arm/qarma.cc
index 4e18b7de23d99cb5e82a76212b3b6b85dddac3c3..5805709cf2755991dca6df079b658ac0bdffacfd 100644 (file)
--- a/src/arch/arm/qarma.cc
+++ b/src/arch/arm/qarma.cc
@@ -42,7 +42,6 @@
 #include "base/bitfield.hh"
 
 using namespace QARMA;
-using namespace std;
 
 
 uint8_t

diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 4d4915b73b7f8879652561484a182584cbd05192..96344a97d87fe326b28721f2bb9a6b76bba0329d 100644 (file)
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -163,7 +163,6 @@
 #include "sim/full_system.hh"
 #include "sim/system.hh"
 
-using namespace std;
 using namespace ArmISA;
 
 static bool

diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index e55df64ad6bb71eaf9d2e7d4b0d4734e5eed4b96..86e4ae52dc1491b3a8ea7a3638801135b4aa5826 100644 (file)
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -42,7 +42,6 @@
 #include "base/bitfield.hh"
 
 using namespace ArmISA;
-using namespace std;
 
 Fault
 SelfDebug::testDebug(ThreadContext *tc, const RequestPtr &req,

diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index bda5ed253c54148a8aa257b7ad84fb3eff2d8e8e..7f5fa1313d0ef781e826586d83dd805fc4ddc872 100644 (file)
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -51,7 +51,6 @@
 #include "dev/arm/gic_v2.hh"
 #include "mem/physical.hh"
 
-using namespace std;
 using namespace Linux;
 using namespace ArmISA;
 

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 91c70884e34baab602bcf1cbb319a3829e9ccce8..6f16f6cf7d4c2694e3f5f99154e75a53d519d735 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -71,7 +71,6 @@
 #include "sim/process.hh"
 #include "sim/pseudo_inst.hh"
 
-using namespace std;
 using namespace ArmISA;
 
 TLB::TLB(const ArmTLBParams &p)

diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index cdb24cac025627c25e62ceb1c43bf688772e7cc5..6521b27377ea5e021de7473140d91a382da834d5 100644 (file)
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -54,7 +54,6 @@
 #include "sim/faults.hh"
 #include "sim/sim_exit.hh"
 
-using namespace std;
 using namespace ArmISA;
 
 namespace Trace {
@@ -68,7 +67,8 @@ TarmacParserRecord::ParserRegEntry TarmacParserRecord::regRecord;
 TarmacParserRecord::ParserMemEntry TarmacParserRecord::memRecord;
 TarmacBaseRecord::TarmacRecordType TarmacParserRecord::currRecordType;
 
-list<TarmacParserRecord::ParserRegEntry> TarmacParserRecord::destRegRecords;
+std::list<TarmacParserRecord::ParserRegEntry>
+    TarmacParserRecord::destRegRecords;
 char TarmacParserRecord::buf[TarmacParserRecord::MaxLineLength];
 TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
 
@@ -737,10 +737,10 @@ TarmacParserRecord::MiscRegMap TarmacParserRecord::miscRegMap = {
 void
 TarmacParserRecord::TarmacParserRecordEvent::process()
 {
-    ostream &outs = Trace::output();
+    std::ostream &outs = Trace::output();
 
-    list<ParserRegEntry>::iterator it = destRegRecords.begin(),
-                                   end = destRegRecords.end();
+    std::list<ParserRegEntry>::iterator it = destRegRecords.begin(),
+                                        end = destRegRecords.end();
 
     std::vector<uint64_t> values;
 
@@ -915,14 +915,14 @@ TarmacParserRecord::TarmacParserRecordEvent::process()
                 TarmacParserRecord::printMismatchHeader(inst, pc);
                 mismatch = true;
             }
-            outs << "diff> [" << it->repr << "] gem5: 0x" << hex;
+            outs << "diff> [" << it->repr << "] gem5: 0x" << std::hex;
             for (auto v : values)
-                outs << setw(16) << setfill('0') << v;
+                outs << std::setw(16) << std::setfill('0') << v;
 
-            outs << ", TARMAC: 0x" << hex;
+            outs << ", TARMAC: 0x" << std::hex;
             for (auto v : it->values)
-                outs << setw(16) << setfill('0') << v;
-            outs << endl;
+                outs << std::setw(16) << std::setfill('0') << v;
+            outs << std::endl;
         }
     }
     destRegRecords.clear();
@@ -947,14 +947,14 @@ void
 TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
                                         ArmISA::PCState pc)
 {
-    ostream &outs = Trace::output();
-    outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick()
-         << " ticks\n"
-         << "[seq_num: " << dec << instRecord.seq_num
-         << ", opcode: 0x" << hex << (staticInst->machInst & 0xffffffff)
+    std::ostream &outs = Trace::output();
+    outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec
+         << curTick() << " ticks\n"
+         << "[seq_num: " << std::dec << instRecord.seq_num
+         << ", opcode: 0x" << std::hex << (staticInst->machInst & 0xffffffff)
          << ", PC: 0x" << pc.pc()
          << ", disasm: " <<  staticInst->disassemble(pc.pc()) << "]"
-         << endl;
+         << std::endl;
 }
 
 TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
@@ -976,7 +976,7 @@ TarmacParserRecord::TarmacParserRecord(Tick _when, ThreadContext *_thread,
 void
 TarmacParserRecord::dump()
 {
-    ostream &outs = Trace::output();
+    std::ostream &outs = Trace::output();
 
     uint64_t written_data = 0;
     unsigned mem_flags = 3 | ArmISA::TLB::AllowUnaligned;
@@ -1005,8 +1005,8 @@ TarmacParserRecord::dump()
                 if (pc.instAddr() != instRecord.addr) {
                     if (!mismatch)
                         printMismatchHeader(staticInst, pc);
-                    outs << "diff> [PC] gem5: 0x" << hex << pc.instAddr()
-                         << ", TARMAC: 0x" << instRecord.addr << endl;
+                    outs << "diff> [PC] gem5: 0x" << std::hex << pc.instAddr()
+                         << ", TARMAC: 0x" << instRecord.addr << std::endl;
                     mismatch = true;
                     mismatchOnPcOrOpcode = true;
                 }
@@ -1014,9 +1014,9 @@ TarmacParserRecord::dump()
                 if (arm_inst->encoding() != instRecord.opcode) {
                     if (!mismatch)
                         printMismatchHeader(staticInst, pc);
-                    outs << "diff> [opcode] gem5: 0x" << hex
+                    outs << "diff> [opcode] gem5: 0x" << std::hex
                          << arm_inst->encoding()
-                         << ", TARMAC: 0x" << instRecord.opcode << endl;
+                         << ", TARMAC: 0x" << instRecord.opcode << std::endl;
                     mismatch = true;
                     mismatchOnPcOrOpcode = true;
                 }
@@ -1049,10 +1049,10 @@ TarmacParserRecord::dump()
                 if (written_data != memRecord.data) {
                     if (!mismatch)
                         printMismatchHeader(staticInst, pc);
-                    outs << "diff> [mem(0x" << hex << memRecord.addr
+                    outs << "diff> [mem(0x" << std::hex << memRecord.addr
                          << ")] gem5: 0x" << written_data
                          << ", TARMAC: 0x" << memRecord.data
-                         << endl;
+                         << std::endl;
                 }
                 break;
 
@@ -1083,8 +1083,8 @@ TarmacParserRecord::dump()
 bool
 TarmacParserRecord::advanceTrace()
 {
-    ifstream& trace = parent.trace;
-    trace >> hex;  // All integer values are in hex base
+    std::ifstream& trace = parent.trace;
+    trace >> std::hex;  // All integer values are in hex base
 
     if (buf[0] != 'I') {
         trace >> buf;
@@ -1201,9 +1201,9 @@ TarmacParserRecord::advanceTrace()
             regRecord.index = miscRegMap[buf];
         } else {
             // Try match with upper case name (misc. register)
-            string reg_name = buf;
-            transform(reg_name.begin(), reg_name.end(), reg_name.begin(),
-                      ::tolower);
+            std::string reg_name = buf;
+            std::transform(reg_name.begin(), reg_name.end(), reg_name.begin(),
+                           ::tolower);
             if (miscRegMap.count(reg_name.c_str())) {
                 regRecord.type = REG_MISC;
                 regRecord.index = miscRegMap[reg_name.c_str()];
@@ -1327,7 +1327,7 @@ TarmacParser::advanceTraceToStartPc()
     Addr pc;
     int saved_offset;
 
-    trace >> hex;  // All integer values are in hex base
+    trace >> std::hex;  // All integer values are in hex base
 
     while (true) {
         saved_offset = trace.tellg();
@@ -1338,7 +1338,7 @@ TarmacParser::advanceTraceToStartPc()
             trace >> buf >> pc;
             if (pc == startPc) {
                 // Set file pointer to the beginning of this line
-                trace.seekg(saved_offset, ios::beg);
+                trace.seekg(saved_offset, std::ios::beg);
                 return;
             } else {
                 trace.ignore(TarmacParserRecord::MaxLineLength, '\n');