cores/spi: fix/simplify loopback

diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py
index 75d8ac12fc0c0b21da558afcd01831f88ae2ed42..6fb1e4680ebf89a4e77d62324f2c127a7184a842 100755 (executable)
--- a/litex/soc/cores/spi.py
+++ b/litex/soc/cores/spi.py
@@ -117,15 +117,16 @@ class SPIMaster(Module, AutoCSR):
         self.sync += \
             If(shift,
                 If(clk_rise,
-                    miso.eq(pads.miso),
+                    If(self.loopback,
+                        miso.eq(pads.mosi)
+                    ).Else(
+                        miso.eq(pads.miso)
+                    )
                 ).Elif(clk_fall,
                     miso_data.eq(Cat(miso, miso_data[:-1]))
                 )
             )
 
-        # Loopback ---------------------------------------------------------------------------------
-        self.comb += If(self.loopback, pads.miso.eq(pads.mosi))
-
     def add_control(self):
         self._control  = CSRStorage(16)
         self._status   = CSRStatus()