case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_fmo) {
- return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN0_EL1);
+ return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
}
break;
}
+ case MISCREG_ICV_IGRPEN0_EL1: {
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+ value = ich_vmcr_el2.VENG0;
+ break;
+ }
+
// Interrupt Group 1 Enable register EL1
case MISCREG_ICC_IGRPEN1:
case MISCREG_ICC_IGRPEN1_EL1: {
if ((currEL() == EL1) && !inSecureState() && hcr_imo) {
- return isa->readMiscRegNoEffect(MISCREG_ICV_IGRPEN1_EL1);
+ return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
}
break;
}
+ case MISCREG_ICV_IGRPEN1_EL1: {
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+ value = ich_vmcr_el2.VENG1;
+ break;
+ }
+
// Interrupt Group 1 Enable register EL3
case MISCREG_ICC_MGRPEN1:
case MISCREG_ICC_IGRPEN1_EL3:
case MISCREG_ICC_PMR:
case MISCREG_ICC_PMR_EL1:
if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
- return isa->readMiscRegNoEffect(MISCREG_ICV_PMR_EL1);
+ return readMiscReg(MISCREG_ICV_PMR_EL1);
}
if (haveEL(EL3) && !inSecureState() &&
break;
+ case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+
+ value = ich_vmcr_el2.VPMR;
+ break;
+ }
+
// Interrupt Acknowledge Register 0
case MISCREG_ICC_IAR0:
case MISCREG_ICC_IAR0_EL1: {
case MISCREG_ICC_PMR:
case MISCREG_ICC_PMR_EL1: {
if ((currEL() == EL1) && !inSecureState() && (hcr_imo || hcr_fmo)) {
- return isa->setMiscRegNoEffect(MISCREG_ICV_PMR_EL1, val);
+ return setMiscReg(MISCREG_ICV_PMR_EL1, val);
}
val &= 0xff;
break;
}
+ case MISCREG_ICV_PMR_EL1: { // Priority Mask Register
+ ICH_VMCR_EL2 ich_vmcr_el2 =
+ isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2);
+ ich_vmcr_el2.VPMR = val & 0xff;
+
+ isa->setMiscRegNoEffect(MISCREG_ICH_VMCR_EL2, ich_vmcr_el2);
+ virtualUpdate();
+ return;
+ }
+
// Interrupt Group 0 Enable Register EL1
case MISCREG_ICC_IGRPEN0:
case MISCREG_ICC_IGRPEN0_EL1: {