Added SPARC_SE simple timing vortex regression.
authorGabe Black <gblack@eecs.umich.edu>
Thu, 29 Mar 2007 17:51:12 +0000 (12:51 -0500)
committerGabe Black <gblack@eecs.umich.edu>
Thu, 29 Mar 2007 17:51:12 +0000 (12:51 -0500)
--HG--
extra : convert_revision : 12a2fc0b43cfa72747c1ef24d124979e43b166c7

tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini [new file with mode: 0644]
tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out [new file with mode: 0644]
tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt [new file with mode: 0644]
tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg [new file with mode: 0644]
tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out [new file with mode: 0644]
tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr [new file with mode: 0644]
tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout [new file with mode: 0644]

diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini
new file mode 100644 (file)
index 0000000..770dac1
--- /dev/null
@@ -0,0 +1,187 @@
+[root]
+type=Root
+children=system
+dummy=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/config.out
new file mode 100644 (file)
index 0000000..30db179
--- /dev/null
@@ -0,0 +1,178 @@
+[root]
+type=Root
+dummy=0
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=vortex bendian.raw
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+input=cin
+output=cout
+env=
+cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt
new file mode 100644 (file)
index 0000000..78f3421
--- /dev/null
@@ -0,0 +1,230 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 473146                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 156372                       # Number of bytes of host memory used
+host_seconds                                   287.96                       # Real time elapsed on the host
+host_tick_rate                                4801122                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                   136246936                       # Number of instructions simulated
+sim_seconds                                  0.001383                       # Number of seconds simulated
+sim_ticks                                  1382530003                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  3575.086285                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2575.086285                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits               37185812                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency      162627100                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.001222                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses                45489                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency    117138100                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.001222                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses           45489                       # number of ReadReq MSHR misses
+system.cpu.dcache.SwapReq_accesses              15916                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_avg_miss_latency  3413.933333                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency  2413.933333                       # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits                  15901                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency          51209                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate          0.000942                       # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses                   15                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency        36209                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate     0.000942                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses              15                       # number of SwapReq MSHR misses
+system.cpu.dcache.WriteReq_accesses          20864304                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  4579.703729                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  3579.703729                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits              20759130                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     481665760                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.005041                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              105174                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency    376491760                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.005041                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         105174                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses            58095605                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  4276.384116                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  3276.384116                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                57944942                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency       644292860                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002593                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses                150663                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency    493629860                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002593                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses           150663                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  4276.384116                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  3276.384116                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits               57944942                       # number of overall hits
+system.cpu.dcache.overall_miss_latency      644292860                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002593                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses               150663                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency    493629860                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002593                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses          150663                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                 146582                       # number of replacements
+system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse               4060.510189                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               33018000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                   107279                       # number of writebacks
+system.cpu.icache.ReadReq_accesses          136246937                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  2909.600795                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  1909.600795                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits              136059913                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency      544165179                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.001373                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency    357141179                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.001373                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs                 727.499749                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses           136246937                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  2909.600795                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  1909.600795                       # average overall mshr miss latency
+system.cpu.icache.demand_hits               136059913                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency       544165179                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.001373                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency    357141179                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.001373                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses          136246937                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  2909.600795                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  1909.600795                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits              136059913                       # number of overall hits
+system.cpu.icache.overall_miss_latency      544165179                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.001373                       # miss rate for overall accesses
+system.cpu.icache.overall_misses               187024                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency    357141179                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.001373                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                 184976                       # number of replacements
+system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse               1952.728312                       # Cycle average of tags in use
+system.cpu.icache.total_refs                136059913                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle             1000315000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses            337636                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  3564.034868                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1961.482636                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                202957                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency     480000652                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.398888                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses              134679                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency    264170520                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.398888                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses         134679                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses          107279                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits              106771                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate       0.004735                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses               508                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate     0.004735                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses          508                       # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  2.299750                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses             337636                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  3564.034868                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1961.482636                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                 202957                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency      480000652                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.398888                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses               134679                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency    264170520                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.398888                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses          134679                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses            444915                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  3550.642088                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1961.482636                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                309728                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency     480000652                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.303849                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses              135187                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency    264170520                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.302707                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses         134679                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements                101911                       # number of replacements
+system.cpu.l2cache.sampled_refs                134679                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse             30685.350019                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  309728                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle             319451000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                   82918                       # number of writebacks
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                       1382530003                       # number of cpu cycles simulated
+system.cpu.num_insts                        136246936                       # Number of instructions executed
+system.cpu.num_refs                          58111522                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls            1946                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg
new file mode 100644 (file)
index 0000000..0ac2d99
--- /dev/null
@@ -0,0 +1,158 @@
+
+  SYSTEM TYPE...
+  __ZTC__                := False 
+  __UNIX__               := True 
+  __RISC__               := True 
+  SPEC_CPU2000_LP64        := False 
+  __MAC__                := False 
+  __BCC__                := False 
+  __BORLANDC__           := False 
+  __GUI__                := False 
+  __WTC__                := False 
+  __HP__                 := False 
+
+  CODE OPTIONS...
+  __MACROIZE_HM__        := True 
+  __MACROIZE_MEM__       := True 
+  ENV01                  := True 
+  USE_HPP_STYPE_HDRS     := False 
+  USE_H_STYPE_HDRS       := False 
+
+  CODE INCLUSION PARAMETERS...
+  INCLUDE_ALL_CODE       := False 
+  INCLUDE_DELETE_CODE    := True 
+  __SWAP_GRP_POS__       := True 
+  __INCLUDE_MTRX__       := False 
+  __BAD_CODE__           := False 
+  API_INCLUDE            := False 
+  BE_CAREFUL             := False 
+  OLDWAY                 := False 
+  NOTUSED                := False 
+
+  SYSTEM PARAMETERS...
+  EXT_ENUM               := 999999999L 
+  CHUNK_CONSTANT         := 55555555 
+  CORE_CONSTANT          := 55555555 
+  CORE_LIMIT             := 20971520 
+  CorePage_Size          := 384000 
+  ALIGN_BYTES            := True 
+  CORE_BLOCK_ALIGN       :=    8 
+  FAR_MEM                := False 
+
+  MEMORY MANAGEMENT PARAMETERS...
+  SYSTEM_ALLOC           := True 
+  SYSTEM_FREESTORE       := True 
+  __NO_DISKCACHE__       := False 
+  __FREEZE_VCHUNKS__     := True 
+  __FREEZE_GRP_PACKETS__ := True 
+  __MINIMIZE_TREE_CACHE__:= True 
+
+  SYSTEM STD PARAMETERS...
+  __STDOUT__             := False 
+  NULL                   :=    0 
+  LPTR                   := False 
+  False_Status           :=    1 
+  True_Status            :=    0 
+  LARGE                  := True 
+  TWOBYTE_BOOL           := False 
+  __NOSTR__              := False 
+
+  MEMORY VALIDATION PARAMETERS...
+  CORE_CRC_CHECK         := False 
+  VALIDATE_MEM_CHUNKS    := False 
+
+  SYSTEM DEBUG OPTIONS...
+  DEBUG                  := False 
+  MCSTAT                 := False 
+  TRACKBACK              := False 
+  FLUSH_FILES            := False 
+  DEBUG_CORE0            := False 
+  DEBUG_RISC             := False 
+  __TREE_BUG__           := False 
+  __TRACK_FILE_READS__   := False 
+  PAGE_SPACE             := False 
+  LEAVE_NO_TRACE         := True 
+  NULL_TRACE_STRS        := False 
+
+  TIME PARAMETERS...
+  CLOCK_IS_LONG          := False 
+  __DISPLAY_TIME__       := False 
+  __TREE_TIME__          := False 
+  __DISPLAY_ERRORS__     := False 
+
+  API MACROS...
+  __BMT01__              := True 
+  OPTIMIZE               := True 
+
+  END OF DEFINES.
+
+
+
+              ...   IMPLODE MEMORY ...
+
+  SWAP to DiskCache := False
+
+  FREEZE_GRP_PACKETS:= True
+
+  QueBug            := 1000
+
+  sizeof(boolean)      =  4
+  sizeof(sizetype)     =  4
+  sizeof(chunkstruc)   = 32
+
+  sizeof(shorttype )   =  2
+  sizeof(idtype    )   =  2
+  sizeof(sizetype  )   =  4
+  sizeof(indextype )   =  4
+  sizeof(numtype   )   =  4
+  sizeof(handletype)   =  4
+  sizeof(tokentype )   =  8
+
+  sizeof(short     )   =  2
+  sizeof(int       )   =  4
+
+  sizeof(lt64      )   =  4
+  sizeof(farlongtype)  =  4
+  sizeof(long      )   =  4
+  sizeof(longaddr  )   =  4
+
+  sizeof(float     )   =  4
+  sizeof(double    )   =  8
+
+  sizeof(addrtype  )   =  4
+  sizeof(char *    )   =  4
+ ALLOC   CORE_1    :: 8
+ BHOOLE NATH
+
+ OPEN File ./input/bendian.rnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @  2030c0
+    DB BlkDirChunk       : Chunk[  10] AT Vbn[3146]
+    DB BlkTknChunk       : Chunk[  11] AT Vbn[3147]
+    DB BlkSizeChunk      : Chunk[  12] AT Vbn[3148]
+ DB Handle Chunk's StackPtr = 20797
+
+  DB[ 1] LOADED;  Handles= 20797
+ KERNEL in CORE[ 1] Restored @ 1b4750
+
+ OPEN File ./input/bendian.wnv 
+    *Status            =   0
+   DB HDR restored from FileVbn[  0]
+    DB BlkDirOffset      : @   21c40
+    DB BlkDirChunk       : Chunk[  31] AT Vbn[ 81]
+    DB BlkTknChunk       : Chunk[  32] AT Vbn[ 82]
+    DB BlkSizeChunk      : Chunk[  33] AT Vbn[ 83]
+ DB Handle Chunk's StackPtr = 17
+
+  DB[ 2] LOADED;  Handles= 17
+ VORTEx_Status == -8 || fffffff8
+
+    BE HERE NOW !!!
+
+
+
+               ... VORTEx ON LINE ...
+
+
+              ...   END OF SESSION ...
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out b/tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out
new file mode 100644 (file)
index 0000000..726b45c
--- /dev/null
@@ -0,0 +1,258 @@
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 3] Created.
+
+VORTEX INPUT PARAMETERS::
+       MESSAGE       FileName:  smred.msg            
+       OUTPUT        FileName:  smred.out            
+       DISK CACHE    FileName:  NULL                 
+       PART DB       FileName:  parts.db             
+       DRAW DB       FileName:  draw.db              
+       PERSON DB     FileName:  emp.db               
+       PERSONS Data  FileName:  ./input/persons.250  
+       PARTS         Count   :  100     
+       OUTER         Loops   :  1       
+       INNER         Loops   :  1       
+       LOOKUP        Parts   :  25      
+       DELETE        Parts   :  10      
+       STUFF         Parts   :  10      
+       DEPTH         Traverse:  5       
+       % DECREASE    Parts   :  0       
+       % INCREASE    LookUps :  0       
+       % INCREASE    Deletes :  0       
+       % INCREASE    Stuffs  :  0       
+       FREEZE_PACKETS        :  1       
+       ALLOC_CHUNKS          :  10000   
+       EXTEND_CHUNKS         :  5000    
+       DELETE Draw objects   :  True                 
+       DELETE Part objects   :  False                
+       QUE_BUG               :  1000
+       VOID_BOUNDARY         :  67108864
+       VOID_RESERVE          :  1048576
+
+       COMMIT_DBS            :  False
+
+
+
+ BMT TEST :: files...
+      EdbName           := PartLib
+      EdbFileName       := parts.db
+      DrwName           := DrawLib
+      DrwFileName       := draw.db
+      EmpName           := PersonLib
+      EmpFileName       := emp.db
+
+      Swap to DiskCache := False
+      Freeze the cache  := True
+
+
+ BMT TEST :: parms...
+      DeBug modulo      := 1000    
+      Create Parts count:= 100     
+      Outer Loops       := 1       
+      Inner Loops       := 1       
+      Look Ups          := 25      
+      Delete Parts      := 10      
+      Stuff Parts       := 10      
+      Traverse Limit    := 5       
+      Delete Draws      := True
+      Delete Parts      := False
+      Delete ALL Parts  := after every <mod  0>Outer Loop
+
+ INITIALIZE LIBRARY ::
+
+ INITIALIZE SCHEMA ::
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 4] Created.
+   PartLibCreate:: Db[  4]; VpartsDir=   1
+
+ Part Count=       1
+
+ Initialize the Class maps
+ LIST HEADS  loaded ... DbListHead_Class = 207
+                        DbListNode_Class = 206
+
+...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
+
+
+...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
+
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 5] Created.
+   DrawLibCreate:: Db[  5]; VpartsDir=   1
+
+ Initialize the Class maps of this schema.
+  Primal_CreateDb Accessed !!!
+ CREATE  Db Header and Db Primal  ... 
+  NEW DB [ 6] Created.
+
+ ***NOTE***  Persons Library Extended!
+
+ Create <131072> Persons.
+ ItNum      0. Person[  6:       5]. Name= Riddell         , Robert V.       ;
+
+ LAST Person Read::
+ ItNum    250. Person[  6:     503]. Name= Gonzales        , Warren X.       ;
+
+ BUILD <Query0>   for <Part2>  class::
+
+  if (link[1].length >=    5) ::
+
+ Build Query2 for <Address>   class::
+
+  if (State == CA || State == T*)
+
+ Build Query1 for <Person>    class::
+
+  if (LastName  >= H* && LastName <= P* && Query0(Residence)) ::
+
+ BUILD <Query3> for <DrawObj>    class::
+
+  if (Id  >= 3000 
+  &&  (Id >= 3000 && Id <= 3001)
+  &&  Id >= 3002)
+
+ BUILD <Query4> for <NamedDrawObj>   class::
+
+  if (Nam ==       Pre*
+  || (Nam ==   ??Mid???  || == Pre??Mid??   || ==     ??Post
+       || ==  Pre??Post  || == ??Mid???Post   || == Pre??Mid???Post)
+  && Id <= 7)
+      SEED          :=    1008; Swap     = False; RgnEntries =   135
+
+ OUTER LOOP [  1] :  NewParts = 100 LookUps = 25 StuffParts = 10.
+
+ Create 100 New Parts
+ Create Part      1. Token[  4:       2].
+
+  <   100> Parts Created. CurrentId=   100
+
+ Connect each instantiated Part TO 3 unique Parts
+ Connect Part      1. Token[  4:       2]
+   Connect  Part     25. Token[  4:      26] FromList=    26.
+   Connect  Part     12. Token[  4:      13] FromList=    13.
+   Connect  Part     59. Token[  4:      60] FromList=    60.
+
+ SET  <DrawObjs>    entries::
+      1. [  5:       5]  := <1       >; @[:     6]
+   Iteration count =   100
+
+ SET  <NamedDrawObjs>  entries::
+      1. [  5:      39]  := <14      >;
+   Iteration count =    12
+
+ SET  <LibRectangles>  entries::
+      1. [  5:      23]  := <8       >; @[:    24]
+   Iteration count =    12
+
+ LIST <DbRectangles>   entries::
+       1. [   5:    23]
+   Iteration count =    12
+
+ SET  <PersonNames  >  entries::
+   Iteration count =   250
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 100
+ <   100> Part            images'  Committed.
+                 <     0> are Named.
+ <    50> Point           images'  Committed.
+ <    81> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  0:       0]. TestObj        Committed.
+ <     0> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  0:       0]. CartesianPoint Committed.
+ <     0> CartesianPoint  images'  Committed.
+
+ BEGIN  Inner Loop Sequence::.
+
+ INNER LOOP [   1:   1] :
+
+ LOOK UP     25 Random Parts and Export each Part.
+
+ LookUp for     26 parts; Asserts =     8
+       <Part2    >  Asserts =     2; NULL Asserts =     3.
+       <DrawObj  >  Asserts =     0; NULL Asserts =     5.
+       <NamedObj >  Asserts =     0; NULL Asserts =     0.
+       <Person   >  Asserts =     0; NULL Asserts =     5.
+       <TestObj  >  Asserts =    60; NULL Asserts =     0.
+
+ DELETE      10 Random Parts.
+
+   PartDelete    :: Token[  4:      91].
+   PartDisconnect:: Token[  4:      91] id:=     90 for each link.
+   DisConnect  link    [   0]:=     50; PartToken[    51:    51].
+   DisConnect  link    [   1]:=     17; PartToken[    18:    18].
+   DisConnect  link    [   2]:=     72; PartToken[    73:    73].
+   DeleteFromList:: Vchunk[ 4:      91]. (*   1)
+   DisConnect  FromList[   0]:=    56;  Token[    57:    57].
+   Vlists[  89] :=   100;
+
+ Delete for     11 parts;
+
+ Traverse Count=     0
+
+ TRAVERSE PartId[     6] and all Connections to  5 Levels
+ SEED In Traverse Part [  4:      65] @ Level =  4.
+
+ Traverse Count=   357
+       Traverse    Asserts =     5. True Tests =     1
+ <     5> DrawObj         objects  DELETED.
+                 <     2> are Named.
+ <     2> Point           objects  DELETED.
+
+ CREATE 10 Additional Parts
+
+ Create 10 New Parts
+ Create Part    101. Token[  4:     102].
+
+  <    10> Parts Created. CurrentId=   110
+
+ Connect each instantiated Part TO 3 unique Parts
+
+ COMMIT All Image copies:: Release=<True>; Max Parts= 110
+ <    81> Part            images'  Committed.
+                 <     0> are Named.
+ <    38> Point           images'  Committed.
+ <    31> Person          images'  Committed.
+
+ COMMIT Parts(*      100)
+
+ Commit TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Committed.
+ <    15> TestObj         images'  Committed.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Committed.
+ <    16> CartesianPoint  images'  Committed.
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ ItNum      0. Token[  3:       4]. TestObj        Deleted.
+ <    15> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ ItNum      0. Token[  3:       3]. CartesianPoint Deleted.
+ <    16> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+
+ END INNER LOOP [   1:   1].
+
+ DELETE All TestObj objects;
+
+ Delete TestObj_Class        in <Primal> DB.
+ <     0> TestObj         objects  Deleted.
+
+ Commit CartesianPoint_Class in <Primal> DB.
+ <     0> CartesianPoint  objects  Deleted.
+
+ DELETE TestObj and Point objects... 
+   STATUS= -201
+V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr
new file mode 100644 (file)
index 0000000..c0f1c1f
--- /dev/null
@@ -0,0 +1,569 @@
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x1838c0 length 0x10.
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+0: system.remote_gdb.listener: listening for remote gdb on port 7001
+warn: Entering event queue @ 0.  Starting simulation...
+warn: Ignoring request to flush register windows.
+warn: ignoring syscall time(4026527856, 4026528256, ...)
+warn: ignoring syscall time(4026527408, 1375098, ...)
+warn: ignoring syscall time(4026527320, 1, ...)
+warn: ignoring syscall time(4026527056, 413, ...)
+warn: ignoring syscall time(4026527056, 414, ...)
+warn: ignoring syscall time(4026527296, 4026527696, ...)
+warn: ignoring syscall time(4026526848, 1375098, ...)
+warn: Increasing stack size by one page.
+warn: ignoring syscall time(4026527056, 409, ...)
+warn: ignoring syscall time(4026527056, 409, ...)
+warn: ignoring syscall time(4026526968, 409, ...)
+warn: ignoring syscall time(4026527048, 409, ...)
+warn: ignoring syscall time(4026527008, 409, ...)
+warn: ignoring syscall time(4026526992, 409, ...)
+warn: ignoring syscall time(4026526992, 409, ...)
+warn: ignoring syscall time(4026526880, 409, ...)
+warn: ignoring syscall time(4026526320, 19045, ...)
+warn: ignoring syscall time(4026526840, 409, ...)
+warn: ignoring syscall time(4026526880, 409, ...)
+warn: ignoring syscall time(4026526880, 409, ...)
+warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(4026526848, 409, ...)
+warn: ignoring syscall time(4026526880, 409, ...)
+warn: ignoring syscall time(4026526864, 409, ...)
+warn: ignoring syscall time(4026526856, 409, ...)
+warn: ignoring syscall time(4026526944, 409, ...)
+warn: ignoring syscall time(4026527016, 4026527416, ...)
+warn: ignoring syscall time(4026526568, 1375098, ...)
+warn: ignoring syscall time(4026527192, 18732, ...)
+warn: ignoring syscall time(4026526640, 409, ...)
+warn: ignoring syscall time(4026526744, 0, ...)
+warn: ignoring syscall time(4026527328, 0, ...)
+warn: ignoring syscall time(4026527752, 225, ...)
+warn: ignoring syscall time(4026527056, 409, ...)
+warn: ignoring syscall time(4026526864, 409, ...)
+warn: ignoring syscall time(4026526880, 409, ...)
+warn: ignoring syscall time(4026527104, 4026527504, ...)
+warn: ignoring syscall time(4026526656, 1375098, ...)
+warn: ignoring syscall time(4026526832, 0, ...)
+warn: ignoring syscall time(4026527328, 0, ...)
+warn: ignoring syscall time(4026527192, 1879089152, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
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+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall times(4026527736, 246, ...)
+warn: ignoring syscall time(4026527480, 1595768, ...)
+warn: ignoring syscall time(4026526920, 17300, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026526920, 19045, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026527480, 0, ...)
+warn: ignoring syscall time(4026526920, 19045, ...)
+warn: ignoring syscall time(4026526920, 17300, ...)
+warn: ignoring syscall time(4026525976, 20500, ...)
+warn: ignoring syscall time(4026525976, 4026526444, ...)
+warn: ignoring syscall time(4026526064, 7004192, ...)
+warn: ignoring syscall time(4026527520, 4, ...)
+warn: ignoring syscall time(4026525768, 0, ...)
diff --git a/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout b/tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout
new file mode 100644 (file)
index 0000000..dc2b618
--- /dev/null
@@ -0,0 +1,13 @@
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 29 2007 03:55:17
+M5 started Thu Mar 29 03:55:38 2007
+M5 executing on zizzer.eecs.umich.edu
+command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
+Global frequency set at 1000000000000 ticks per second
+Exiting @ tick 1382530003 because target called exit()