replace freg_t typedef with actual sv_freg_t class derived from sv_regbase_t

diff --git a/riscv/insns/c_fsd.h b/riscv/insns/c_fsd.h
index 3b8e040809555656fe62b6ed2d3ecf45898c0274..d038d9a03e959c3d5b41b864b8656c44051d393a 100644 (file)
--- a/riscv/insns/c_fsd.h
+++ b/riscv/insns/c_fsd.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), RVC_FRS2S.v[0]);
+MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), ((freg_t)RVC_FRS2S).v[0]);

diff --git a/riscv/insns/c_fsdsp.h b/riscv/insns/c_fsdsp.h
index 1a4d50c3b3989391dff11394c8ec090acc24b141..ab3c69b83a396a823a08d128de91cf51e79f5368 100644 (file)
--- a/riscv/insns/c_fsdsp.h
+++ b/riscv/insns/c_fsdsp.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_FRS2.v[0]);
+MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), ((freg_t)RVC_FRS2).v[0]);

diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h
index e400d727cfaf0eb3339c534ba439aeebeeb7b35a..2f032109f614c1ac7104326f376870b584ec55e9 100644 (file)
--- a/riscv/insns/c_fsw.h
+++ b/riscv/insns/c_fsw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()), RVC_FRS2S.v[0]);
+  MMU.store_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()), ((freg_t)RVC_FRS2S).v[0]);
 } else { // c.sd
   MMU.store_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()), RVC_RS2S);
 }

diff --git a/riscv/insns/c_fswsp.h b/riscv/insns/c_fswsp.h
index cbf92641054ef7fa3e53de7a2e977189d4eec6da..fff75fccd45059f043cb5a131cec3d3dea396edd 100644 (file)
--- a/riscv/insns/c_fswsp.h
+++ b/riscv/insns/c_fswsp.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), RVC_FRS2.v[0]);
+  MMU.store_uint32(rv_add(RVC_SP, insn.rvc_swsp_imm()), ((freg_t)RVC_FRS2).v[0]);
 } else { // c.sdsp
   MMU.store_uint64(rv_add(RVC_SP, insn.rvc_sdsp_imm()), RVC_RS2);
 }

diff --git a/riscv/insns/fmv_x_d.h b/riscv/insns/fmv_x_d.h
index e1a23f482735b1dd97221b0f69eeaa2bcc98e39a..e292ed04413068292f2e35b820bef804c495f871 100644 (file)
--- a/riscv/insns/fmv_x_d.h
+++ b/riscv/insns/fmv_x_d.h
@@ -1,4 +1,4 @@
 require_extension('D');
 require_rv64;
 require_fp;
-WRITE_RD(FRS1.v[0]);
+WRITE_RD(((freg_t)FRS1).v[0]);

diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index ca23310b3a5f195220f90a09368c5aa821d9a913..987ce7b33dcd7bf29f7ed4f8a430efd9d004e5a3 100644 (file)
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(sv_reg_t(FRS1.v[0])));
+WRITE_RD(sext32(sv_reg_t(((freg_t)FRS1).v[0])));

diff --git a/riscv/insns/fsd.h b/riscv/insns/fsd.h
index f1a76ab7a6b4291f00ec0209f65058b206396b5e..038380644a2f833c52c9494e6c214712db99965f 100644 (file)
--- a/riscv/insns/fsd.h
+++ b/riscv/insns/fsd.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-MMU.store_uint64(rv_add(RS1, insn.s_imm()), FRS2.v[0]);
+MMU.store_uint64(rv_add(RS1, insn.s_imm()), ((freg_t)FRS2).v[0]);

diff --git a/riscv/insns/fsw.h b/riscv/insns/fsw.h
index 226e30e006793d03c60b3334bd5fc5477eaf567a..d1252464cf7bad3cae47aa085333a1a0e6fda770 100644 (file)
--- a/riscv/insns/fsw.h
+++ b/riscv/insns/fsw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-MMU.store_uint32(rv_add(RS1, insn.s_imm()), FRS2.v[0]);
+MMU.store_uint32(rv_add(RS1, insn.s_imm()), ((freg_t)FRS2).v[0]);

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 5c5d6285884f47b111fba2f00a57112fbc2e46cb..e93ace47245c4143f40c8f1bed8aedf028079612 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -17,7 +17,7 @@ void (sv_proc_t::WRITE_FRD)(sv_float64_t value)
 
 void (sv_proc_t::WRITE_FRD)(sv_freg_t value)
 {
-    fprintf(stderr, "WRITE_FRD fsv_reg_t %lx\n", value.v[0]);
+    fprintf(stderr, "WRITE_FRD fsv_reg_t %lx\n", ((freg_t)value).v[0]);
     DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 90f2791126da9435400d1116fd143b85cf26b193..56cf9a86441827474cf322fc95c6e00d6c2067a4 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -59,7 +59,7 @@ class insn_t;
 typedef float32_t sv_float32_t;
 typedef float64_t sv_float64_t;
 typedef float128_t sv_float128_t;
-typedef freg_t sv_freg_t;
+//typedef freg_t sv_freg_t;
 
 class sv_proc_t
 {

diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 8bdc940f50f8d8e9539403bd2026b601dd7036cb..b6f003e5d67741abf7624240466caae5263121d1 100644 (file)
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -75,4 +75,20 @@ public:
 inline sv_reg_t::operator sv_sreg_t() const &
 { return sv_sreg_t((int64_t)reg, elwidth); }
 
+class sv_freg_t : public sv_regbase_t {
+public:
+    sv_freg_t(freg_t _reg) : sv_regbase_t(), reg(_reg) { } // default elwidth
+    sv_freg_t(freg_t _reg, uint8_t _elwidth) :
+                sv_regbase_t(_elwidth), reg(_reg)
+                                                {}
+    sv_freg_t(freg_t _reg, int xlen, uint8_t _elwidth) :
+                sv_regbase_t(xlen, _elwidth), reg(_reg)
+                                                {}
+
+    freg_t reg;
+public:
+
+  operator freg_t() const& { return reg; }
+};
+
 #endif