fatal_if(!tlb, "Table walker must have a valid TLB\n");
}
-BaseMasterPort&
-TableWalker::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+TableWalker::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port") {
if (!isStage2) {
fatal("Cannot access table walker port through stage-two walker\n");
}
}
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
TableWalker::WalkerState::WalkerState() :
DrainState drain() override;
void drainResume() override;
- BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void regStats() override;
return fault;
}
-BaseMasterPort*
-TLB::getTableWalkerMasterPort()
+Port *
+TLB::getTableWalkerPort()
{
return &stage2Mmu->getPort();
}
void regProbePoints() override;
/**
- * Get the table walker master port. This is used for migrating
+ * Get the table walker port. This is used for migrating
* port connections during a CPU takeOverFrom() call. For
* architectures that do not have a table walker, NULL is
* returned, hence the use of a pointer rather than a
*
* @return A pointer to the walker master port
*/
- BaseMasterPort* getTableWalkerMasterPort() override;
+ Port *getTableWalkerPort() override;
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
virtual void takeOverFrom(BaseTLB *otlb) = 0;
/**
- * Get the table walker master port if present. This is used for
+ * Get the table walker port if present. This is used for
* migrating port connections during a CPU takeOverFrom()
* call. For architectures that do not have a table walker, NULL
* is returned, hence the use of a pointer rather than a
* reference.
*
- * @return A pointer to the walker master port or NULL if not present
+ * @return A pointer to the walker port or NULL if not present
*/
- virtual BaseMasterPort* getTableWalkerMasterPort() { return NULL; }
+ virtual Port* getTableWalkerPort() { return NULL; }
void memInvalidate() { flushAll(); }
};
AddrRangeList getIntAddrRange() const override;
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override
{
if (if_name == "int_master") {
return intMasterPort;
- }
- return BasicPioDevice::getMasterPort(if_name, idx);
- }
-
- BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID) override
- {
- if (if_name == "int_slave") {
+ } else if (if_name == "int_slave") {
return intSlavePort;
}
- return BasicPioDevice::getSlavePort(if_name, idx);
+ return BasicPioDevice::getPort(if_name, idx);
}
/*
}
-BaseMasterPort &
-Walker::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+Walker::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port")
return port;
else
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
const RequestPtr &req, BaseTLB::Mode mode);
Fault startFunctional(ThreadContext * _tc, Addr &addr,
unsigned &logBytes, BaseTLB::Mode mode);
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
protected:
// The TLB we're supposed to load.
}
}
-BaseMasterPort *
-TLB::getTableWalkerMasterPort()
+Port *
+TLB::getTableWalkerPort()
{
- return &walker->getMasterPort("port");
+ return &walker->getPort("port");
}
} // namespace X86ISA
void unserialize(CheckpointIn &cp) override;
/**
- * Get the table walker master port. This is used for
+ * Get the table walker port. This is used for
* migrating port connections during a CPU takeOverFrom()
* call. For architectures that do not have a table walker,
* NULL is returned, hence the use of a pointer rather than a
* reference. For X86 this method will always return a valid
* port pointer.
*
- * @return A pointer to the walker master port
+ * @return A pointer to the walker port
*/
- BaseMasterPort *getTableWalkerMasterPort() override;
+ Port *getTableWalkerPort() override;
};
}
threadContexts[0]->regStats(name());
}
-BaseMasterPort &
-BaseCPU::getMasterPort(const string &if_name, PortID idx)
+Port &
+BaseCPU::getPort(const string &if_name, PortID idx)
{
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
- // of getDataPort and getInstPort. In all cases there methods
- // return a MasterPort pointer.
+ // of getDataPort and getInstPort.
if (if_name == "dcache_port")
return getDataPort();
else if (if_name == "icache_port")
return getInstPort();
else
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
ThreadContext::compare(oldTC, newTC);
*/
- BaseMasterPort *old_itb_port =
- oldTC->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *old_dtb_port =
- oldTC->getDTBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_itb_port =
- newTC->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_dtb_port =
- newTC->getDTBPtr()->getTableWalkerMasterPort();
+ Port *old_itb_port = oldTC->getITBPtr()->getTableWalkerPort();
+ Port *old_dtb_port = oldTC->getDTBPtr()->getTableWalkerPort();
+ Port *new_itb_port = newTC->getITBPtr()->getTableWalkerPort();
+ Port *new_dtb_port = newTC->getDTBPtr()->getTableWalkerPort();
// Move over any table walker ports if they exist
if (new_itb_port) {
assert(!new_itb_port->isConnected());
assert(old_itb_port);
assert(old_itb_port->isConnected());
- BaseSlavePort &slavePort = old_itb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_itb_port)->getSlavePort();
old_itb_port->unbind();
new_itb_port->bind(slavePort);
}
assert(!new_dtb_port->isConnected());
assert(old_dtb_port);
assert(old_dtb_port->isConnected());
- BaseSlavePort &slavePort = old_dtb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_dtb_port)->getSlavePort();
old_dtb_port->unbind();
new_dtb_port->bind(slavePort);
}
CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
if (oldChecker && newChecker) {
- BaseMasterPort *old_checker_itb_port =
- oldChecker->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *old_checker_dtb_port =
- oldChecker->getDTBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_checker_itb_port =
- newChecker->getITBPtr()->getTableWalkerMasterPort();
- BaseMasterPort *new_checker_dtb_port =
- newChecker->getDTBPtr()->getTableWalkerMasterPort();
+ Port *old_checker_itb_port =
+ oldChecker->getITBPtr()->getTableWalkerPort();
+ Port *old_checker_dtb_port =
+ oldChecker->getDTBPtr()->getTableWalkerPort();
+ Port *new_checker_itb_port =
+ newChecker->getITBPtr()->getTableWalkerPort();
+ Port *new_checker_dtb_port =
+ newChecker->getDTBPtr()->getTableWalkerPort();
newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
assert(!new_checker_itb_port->isConnected());
assert(old_checker_itb_port);
assert(old_checker_itb_port->isConnected());
- BaseSlavePort &slavePort =
- old_checker_itb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_checker_itb_port)->
+ getSlavePort();
old_checker_itb_port->unbind();
new_checker_itb_port->bind(slavePort);
}
assert(!new_checker_dtb_port->isConnected());
assert(old_checker_dtb_port);
assert(old_checker_dtb_port->isConnected());
- BaseSlavePort &slavePort =
- old_checker_dtb_port->getSlavePort();
+ auto &slavePort =
+ dynamic_cast<BaseMasterPort *>(old_checker_dtb_port)->
+ getSlavePort();
old_checker_dtb_port->unbind();
new_checker_dtb_port->bind(slavePort);
}
// we are switching to.
assert(!getInstPort().isConnected());
assert(oldCPU->getInstPort().isConnected());
- BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
+ auto &inst_peer_port =
+ dynamic_cast<BaseMasterPort &>(oldCPU->getInstPort()).getSlavePort();
oldCPU->getInstPort().unbind();
getInstPort().bind(inst_peer_port);
assert(!getDataPort().isConnected());
assert(oldCPU->getDataPort().isConnected());
- BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
+ auto &data_peer_port =
+ dynamic_cast<BaseMasterPort &>(oldCPU->getDataPort()).getSlavePort();
oldCPU->getDataPort().unbind();
getDataPort().bind(data_peer_port);
}
MasterID instMasterId() { return _instMasterId; }
/**
- * Get a master port on this CPU. All CPUs have a data and
+ * Get a port on this CPU. All CPUs have a data and
* instruction port, and this method uses getDataPort and
* getInstPort of the subclasses to resolve the two ports.
*
*
* @return a reference to the port with the given name
*/
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/** Get cpu task id */
uint32_t taskId() const { return _taskId; }
generator->setDirectedTester(this);
}
-BaseMasterPort &
-RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+RubyDirectedTester::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "cpuPort") {
// pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
} else {
if (idx >= static_cast<int>(ports.size())) {
- panic("RubyDirectedTester::getMasterPort: unknown index %d\n", idx);
+ panic("RubyDirectedTester::getPort: unknown index %d\n", idx);
}
return *ports[idx];
RubyDirectedTester(const Params *p);
~RubyDirectedTester();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
MasterPort* getCpuPort(int idx);
name(), id);
}
-BaseMasterPort &
-GarnetSyntheticTraffic::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+GarnetSyntheticTraffic::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "test")
return cachePort;
else
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
// main simulation loop (one cycle)
void tick();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* Print state of address in memory system via PrintReq (for
schedule(noResponseEvent, clockEdge(progressCheck));
}
-BaseMasterPort &
-MemTest::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+MemTest::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port")
return port;
else
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
virtual void regStats();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
protected:
m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this);
}
-BaseMasterPort &
-RubyTester::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+RubyTester::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "cpuInstPort" && if_name != "cpuInstDataPort" &&
if_name != "cpuDataPort") {
// pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
} else {
if (if_name == "cpuInstPort") {
if (idx > m_num_inst_only_ports) {
- panic("RubyTester::getMasterPort: unknown inst port %d\n",
+ panic("RubyTester::getPort: unknown inst port %d\n",
idx);
}
//
return *readPorts[idx];
} else if (if_name == "cpuInstDataPort") {
if (idx > m_num_inst_data_ports) {
- panic("RubyTester::getMasterPort: unknown inst+data port %d\n",
+ panic("RubyTester::getPort: unknown inst+data port %d\n",
idx);
}
int read_idx = idx + m_num_inst_only_ports;
//
if (idx > (static_cast<int>(readPorts.size()) -
(m_num_inst_only_ports + m_num_inst_data_ports))) {
- panic("RubyTester::getMasterPort: unknown data port %d\n",
+ panic("RubyTester::getPort: unknown data port %d\n",
idx);
}
int read_idx = idx + m_num_inst_only_ports + m_num_inst_data_ports;
RubyTester(const Params *p);
~RubyTester();
- virtual BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
bool isInstOnlyCpuPort(int idx);
bool isInstDataCpuPort(int idx);
{
}
-BaseMasterPort&
-BaseTrafficGen::getMasterPort(const string& if_name, PortID idx)
+Port &
+BaseTrafficGen::getPort(const string &if_name, PortID idx)
{
if (if_name == "port") {
return port;
} else {
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
~BaseTrafficGen();
- BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void init() override;
// Unbind the ports of the old CPU and bind the ports of the TraceCPU.
assert(!getInstPort().isConnected());
assert(oldCPU->getInstPort().isConnected());
- BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort();
+ Port &inst_peer_port = oldCPU->getInstPort().getSlavePort();
oldCPU->getInstPort().unbind();
getInstPort().bind(inst_peer_port);
assert(!getDataPort().isConnected());
assert(oldCPU->getDataPort().isConnected());
- BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort();
+ Port &data_peer_port = oldCPU->getDataPort().getSlavePort();
oldCPU->getDataPort().unbind();
getDataPort().bind(data_peer_port);
}
panic("Unknown memory mode.");
}
-BaseMasterPort &
-DmaDevice::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+DmaDevice::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "dma") {
return dmaPort;
}
- return PioDevice::getMasterPort(if_name, idx);
+ return PioDevice::getPort(if_name, idx);
}
unsigned int cacheBlockSize() const { return sys->cacheLineSize(); }
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
};
pioPort.sendRangeChange();
}
-BaseSlavePort &
-PioDevice::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+PioDevice::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "pio") {
return pioPort;
}
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
BasicPioDevice::BasicPioDevice(const Params *p, Addr size)
virtual void init();
- virtual BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
friend class PioPort;
class EtherLink(SimObject):
type = 'EtherLink'
cxx_header = "dev/net/etherlink.hh"
- cxx_extra_bases = [ "EtherObject" ]
int0 = SlavePort("interface 0")
int1 = SlavePort("interface 1")
delay = Param.Latency('0us', "packet transmit delay")
class DistEtherLink(SimObject):
type = 'DistEtherLink'
cxx_header = "dev/net/dist_etherlink.hh"
- cxx_extra_bases = [ "EtherObject" ]
int0 = SlavePort("interface 0")
delay = Param.Latency('0us', "packet transmit delay")
delay_var = Param.Latency('0ns', "packet transmit delay variability")
class EtherBus(SimObject):
type = 'EtherBus'
cxx_header = "dev/net/etherbus.hh"
- cxx_extra_bases = [ "EtherObject" ]
loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
class EtherSwitch(SimObject):
type = 'EtherSwitch'
cxx_header = "dev/net/etherswitch.hh"
- cxx_extra_bases = [ "EtherObject" ]
dump = Param.EtherDump(NULL, "dump object")
fabric_speed = Param.NetworkBandwidth('10Gbps', "switch fabric speed in bits "
"per second")
type = 'EtherTapBase'
abstract = True
cxx_header = "dev/net/ethertap.hh"
- cxx_extra_bases = [ "EtherObject" ]
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
tap = SlavePort("Ethernet interface to connect to gem5's network")
type = 'EtherDevice'
abstract = True
cxx_header = "dev/net/etherdevice.hh"
- cxx_extra_bases = [ "EtherObject" ]
interface = MasterPort("Ethernet Interface")
class IGbE(EtherDevice):
Import('*')
SimObject('Ethernet.py')
-Source('python.cc', add_tags='python')
# Basic Ethernet infrastructure
Source('etherbus.cc')
#include "dev/net/etherdump.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherlink.hh"
-#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "dev/net/tcp_iface.hh"
#include "params/EtherLink.hh"
delete distIface;
}
-EtherInt*
-DistEtherLink::getEthPort(const std::string &if_name, int idx)
+Port &
+DistEtherLink::getPort(const std::string &if_name, PortID idx)
{
- if (if_name != "int0") {
- return nullptr;
- } else {
- panic_if(localIface->getPeer(), "interface already connected to");
- }
- return localIface;
+ if (if_name == "int0")
+ return *localIface;
+ return SimObject::getPort(if_name, idx);
}
void
#include <iostream>
#include "dev/net/etherlink.hh"
-#include "dev/net/etherobject.hh"
#include "params/DistEtherLink.hh"
class DistIface;
/**
* Model for a fixed bandwidth full duplex ethernet link.
*/
-class DistEtherLink : public SimObject, public EtherObject
+class DistEtherLink : public SimObject
{
protected:
class LocalIface;
return dynamic_cast<const Params *>(_params);
}
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
virtual void init() override;
virtual void startup() override;
packet = 0;
}
-EtherInt*
-EtherBus::getEthPort(const std::string &if_name, int idx)
+Port &
+EtherBus::getPort(const std::string &if_name, PortID idx)
{
panic("Etherbus doesn't work\n");
}
#ifndef __DEV_NET_ETHERBUS_HH__
#define __DEV_NET_ETHERBUS_HH__
-#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherBus.hh"
#include "sim/eventq.hh"
class EtherDump;
class EtherInt;
-class EtherBus : public SimObject, public EtherObject
+class EtherBus : public SimObject
{
protected:
typedef std::list<EtherInt *> devlist_t;
void reg(EtherInt *dev);
bool busy() const { return (bool)packet; }
bool send(EtherInt *sender, EthPacketPtr &packet);
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
};
#endif // __DEV_NET_ETHERBUS_HH__
#define __DEV_NET_ETHERDEVICE_HH__
#include "base/statistics.hh"
-#include "dev/net/etherobject.hh"
#include "dev/pci/device.hh"
#include "params/EtherDevBase.hh"
#include "params/EtherDevice.hh"
class EtherInt;
-class EtherDevice : public PciDevice, public EtherObject
+class EtherDevice : public PciDevice
{
public:
typedef EtherDeviceParams Params;
delete interface[1];
}
-EtherInt*
-EtherLink::getEthPort(const std::string &if_name, int idx)
+Port &
+EtherLink::getPort(const std::string &if_name, PortID idx)
{
- Interface *i;
if (if_name == "int0")
- i = interface[0];
+ return *interface[0];
else if (if_name == "int1")
- i = interface[1];
- else
- return NULL;
- if (i->getPeer())
- panic("interface already connected to\n");
-
- return i;
+ return *interface[1];
+ return SimObject::getPort(if_name, idx);
}
#include "base/types.hh"
#include "dev/net/etherint.hh"
-#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "params/EtherLink.hh"
#include "sim/eventq.hh"
/*
* Model for a fixed bandwidth full duplex ethernet link
*/
-class EtherLink : public EtherObject, public SimObject
+class EtherLink : public SimObject
{
protected:
class Interface;
return dynamic_cast<const Params *>(_params);
}
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
+++ /dev/null
-/*
- * Copyright (c) 2007 The Regents of The University of Michigan
- * Copyright 2019 Google, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- * Gabe Black
- */
-
-/**
- * @file
- * Base Ethernet Object declaration.
- */
-
-#ifndef __DEV_NET_ETHEROBJECT_HH__
-#define __DEV_NET_ETHEROBJECT_HH__
-
-#include <string>
-
-class EtherInt;
-
-/**
- * The base EtherObject interface.
- */
-class EtherObject
-{
- public:
- virtual EtherInt *getEthPort(const std::string &if_name, int idx=-1) = 0;
-};
-
-#endif // __DEV_NET_ETHEROBJECT_HH__
interfaces.clear();
}
-EtherInt*
-EtherSwitch::getEthPort(const std::string &if_name, int idx)
+Port &
+EtherSwitch::getPort(const std::string &if_name, PortID idx)
{
- if (idx < 0 || idx >= interfaces.size())
- return nullptr;
-
- Interface *interface = interfaces.at(idx);
- panic_if(interface->getPeer(), "interface already connected\n");
+ if (if_name == "interface") {
+ panic_if(idx < 0 || idx >= interfaces.size(), "index out of bounds");
+ return *interfaces.at(idx);
+ }
- return interface;
+ return SimObject::getPort(if_name, idx);
}
bool
#include "base/inet.hh"
#include "dev/net/etherint.hh"
#include "dev/net/etherlink.hh"
-#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#include "dev/net/pktfifo.hh"
#include "params/EtherSwitch.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
-class EtherSwitch : public SimObject, public EtherObject
+class EtherSwitch : public SimObject
{
public:
typedef EtherSwitchParams Params;
return dynamic_cast<const Params*>(_params);
}
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
protected:
/**
}
-EtherInt*
-EtherTapBase::getEthPort(const std::string &if_name, int idx)
+Port &
+EtherTapBase::getPort(const std::string &if_name, PortID idx)
{
- if (if_name == "tap") {
- if (interface->getPeer())
- panic("Interface already connected to\n");
- return interface;
- }
- return NULL;
+ if (if_name == "tap")
+ return *interface;
+ return SimObject::getPort(if_name, idx);
}
bool
#include "base/pollevent.hh"
#include "config/use_tuntap.hh"
#include "dev/net/etherint.hh"
-#include "dev/net/etherobject.hh"
#include "dev/net/etherpkt.hh"
#if USE_TUNTAP
class TapEvent;
class EtherTapInt;
-class EtherTapBase : public SimObject, public EtherObject
+class EtherTapBase : public SimObject
{
public:
typedef EtherTapBaseParams Params;
EtherTapInt *interface;
public:
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
bool recvSimulated(EthPacketPtr packet);
void sendSimulated(void *data, size_t len);
PciDevice::init();
}
-EtherInt*
-IGbE::getEthPort(const std::string &if_name, int idx)
+Port &
+IGbE::getPort(const std::string &if_name, PortID idx)
{
-
- if (if_name == "interface") {
- if (etherInt->getPeer())
- panic("Port already connected to\n");
- return etherInt;
- }
- return NULL;
+ if (if_name == "interface")
+ return *etherInt;
+ return EtherDevice::getPort(if_name, idx);
}
Tick
~IGbE();
void init() override;
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
Tick lastInterrupt;
return configDelay;
}
-EtherInt*
-NSGigE::getEthPort(const std::string &if_name, int idx)
+Port &
+NSGigE::getPort(const std::string &if_name, PortID idx)
{
- if (if_name == "interface") {
- if (interface->getPeer())
- panic("interface already connected to\n");
- return interface;
- }
- return NULL;
+ if (if_name == "interface")
+ return *interface;
+ return EtherDevBase::getPort(if_name, idx);
}
/**
NSGigE(Params *params);
~NSGigE();
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
Tick writeConfig(PacketPtr pkt) override;
+++ /dev/null
-/*
- * Copyright 2019 Google, Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "python/pybind11/pybind.hh"
-
-#include "dev/net/etherobject.hh"
-#include "sim/init.hh"
-
-namespace
-{
-
-void
-ethernet_pybind(pybind11::module &m_internal)
-{
- pybind11::module m = m_internal.def_submodule("ethernet");
- pybind11::class_<
- EtherObject, std::unique_ptr<EtherObject, pybind11::nodelete>>(
- m, "EtherObject");
-}
-EmbeddedPyBind embed_("ethernet", ðernet_pybind);
-
-} // anonymous namespace
_maxVnicDistance = 0;
}
-EtherInt*
-Device::getEthPort(const std::string &if_name, int idx)
+Port &
+Device::getPort(const std::string &if_name, PortID idx)
{
- if (if_name == "interface") {
- if (interface->getPeer())
- panic("interface already connected to\n");
-
- return interface;
- }
- return NULL;
+ if (if_name == "interface")
+ return *interface;
+ return EtherDevBase::getPort(if_name, idx);
}
public:
bool recvPacket(EthPacketPtr packet);
void transferDone();
- EtherInt *getEthPort(const std::string &if_name, int idx) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* DMA parameters
delete [] copyBuffer;
}
-BaseMasterPort &
-CopyEngine::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+CopyEngine::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "dma") {
// pass it along to our super class
- return PciDevice::getMasterPort(if_name, idx);
+ return PciDevice::getPort(if_name, idx);
} else {
if (idx >= static_cast<int>(chan.size())) {
- panic("CopyEngine::getMasterPort: unknown index %d\n", idx);
+ panic("CopyEngine::getPort: unknown index %d\n", idx);
}
- return chan[idx]->getMasterPort();
+ return chan[idx]->getPort();
}
}
-BaseMasterPort &
-CopyEngine::CopyEngineChannel::getMasterPort()
+Port &
+CopyEngine::CopyEngineChannel::getPort()
{
return cePort;
}
public:
CopyEngineChannel(CopyEngine *_ce, int cid);
virtual ~CopyEngineChannel();
- BaseMasterPort &getMasterPort();
+ Port &getPort();
std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); }
virtual Tick read(PacketPtr pkt)
void regStats() override;
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx = InvalidPortID) override;
Tick read(PacketPtr pkt) override;
Tick write(PacketPtr pkt) override;
IntDevice::init();
}
-BaseMasterPort &
-X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "int_master")
return intMasterPort;
- return BasicPioDevice::getMasterPort(if_name, idx);
+ return BasicPioDevice::getPort(if_name, idx);
}
AddrRangeList
void writeReg(uint8_t offset, uint32_t value);
uint32_t readReg(uint8_t offset);
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
Tick recvResponse(PacketPtr pkt) override;
// port to the SQC TLB (there's a separate TLB for each I-cache)
ITLBPort *sqcTLBPort;
- virtual BaseMasterPort&
- getMasterPort(const std::string &if_name, PortID idx)
+ Port &
+ getPort(const std::string &if_name, PortID idx) override
{
if (if_name == "memory_port") {
memPort[idx] = new DataPort(csprintf("%s-port%d", name(), idx),
}
-BaseMasterPort&
-GpuDispatcher::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+GpuDispatcher::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "translation_port") {
return *tlbPort;
}
- return DmaDevice::getMasterPort(if_name, idx);
+ return DmaDevice::getPort(if_name, idx);
}
void
TLBPort *tlbPort;
- virtual BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
AddrRangeList getAddrRanges() const;
Tick read(PacketPtr pkt);
assert(translationReturnEvent.empty());
}
- BaseSlavePort&
- GpuTLB::getSlavePort(const std::string &if_name, PortID idx)
+ Port &
+ GpuTLB::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "slave") {
if (idx >= static_cast<PortID>(cpuSidePort.size())) {
- panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *cpuSidePort[idx];
- } else {
- panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name);
- }
- }
-
- BaseMasterPort&
- GpuTLB::getMasterPort(const std::string &if_name, PortID idx)
- {
- if (if_name == "master") {
+ } else if (if_name == "master") {
if (idx >= static_cast<PortID>(memSidePort.size())) {
- panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
hasMemSidePort = true;
return *memSidePort[idx];
} else {
- panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name);
+ panic("TLBCoalescer::getPort: unknown port %s\n", if_name);
}
}
// TLB ports on the memory side
std::vector<MemSidePort*> memSidePort;
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx=InvalidPortID);
-
- BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx=InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* TLB TranslationState: this currently is a somewhat bastardization of
return range;
}
- virtual BaseSlavePort &
- getSlavePort(const std::string& if_name, PortID idx)
+ Port &
+ getPort(const std::string &if_name, PortID idx)
{
if (if_name == "cuPort") {
// TODO need to set name dynamically at this point?
}
}
-BaseSlavePort&
-TLBCoalescer::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+TLBCoalescer::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "slave") {
if (idx >= static_cast<PortID>(cpuSidePort.size())) {
- panic("TLBCoalescer::getSlavePort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *cpuSidePort[idx];
- } else {
- panic("TLBCoalescer::getSlavePort: unknown port %s\n", if_name);
- }
-}
-
-BaseMasterPort&
-TLBCoalescer::getMasterPort(const std::string &if_name, PortID idx)
-{
- if (if_name == "master") {
+ } else if (if_name == "master") {
if (idx >= static_cast<PortID>(memSidePort.size())) {
- panic("TLBCoalescer::getMasterPort: unknown index %d\n", idx);
+ panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *memSidePort[idx];
} else {
- panic("TLBCoalescer::getMasterPort: unknown port %s\n", if_name);
+ panic("TLBCoalescer::getPort: unknown port %s\n", if_name);
}
}
// Coalescer master ports on the memory side
std::vector<MemSidePort*> memSidePort;
- BaseMasterPort& getMasterPort(const std::string &if_name, PortID idx);
- BaseSlavePort& getSlavePort(const std::string &if_name, PortID idx);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void processProbeTLBEvent();
/// This event issues the TLB probes
}
}
-BaseMasterPort&
-SimpleCache::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+SimpleCache::getPort(const std::string &if_name, PortID idx)
{
panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
// This is the name from the Python SimObject declaration in SimpleCache.py
if (if_name == "mem_side") {
return memPort;
- } else {
- // pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort&
-SimpleCache::getSlavePort(const std::string& if_name, PortID idx)
-{
- // This is the name from the Python SimObject declaration (SimpleMemobj.py)
- if (if_name == "cpu_side" && idx < cpuPorts.size()) {
+ } else if (if_name == "cpu_side" && idx < cpuPorts.size()) {
// We should have already created all of the ports in the constructor
return cpuPorts[idx];
} else {
// pass it along to our super class
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
SimpleCache(SimpleCacheParams *params);
/**
- * Get a master port with a given name and index. This is used at
+ * Get a port with a given name and index. This is used at
* binding time and returns a reference to a protocol-agnostic
- * base master port.
+ * port.
*
* @param if_name Port name
* @param idx Index in the case of a VectorPort
*
* @return A reference to the given port
*/
- virtual BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
-
- /**
- * Get a slave port with a given name and index. This is used at
- * binding time and returns a reference to a protocol-agnostic
- * base master port.
- *
- * @param if_name Port name
- * @param idx Index in the case of a VectorPort
- *
- * @return A reference to the given port
- */
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* Register the stats
{
}
-BaseMasterPort&
-SimpleMemobj::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+SimpleMemobj::getPort(const std::string &if_name, PortID idx)
{
panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
// This is the name from the Python SimObject declaration (SimpleMemobj.py)
if (if_name == "mem_side") {
return memPort;
- } else {
- // pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort&
-SimpleMemobj::getSlavePort(const std::string& if_name, PortID idx)
-{
- panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
-
- // This is the name from the Python SimObject declaration in SimpleCache.py
- if (if_name == "inst_port") {
+ } else if (if_name == "inst_port") {
return instPort;
} else if (if_name == "data_port") {
return dataPort;
} else {
// pass it along to our super class
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
SimpleMemobj(SimpleMemobjParams *params);
/**
- * Get a master port with a given name and index. This is used at
+ * Get a port with a given name and index. This is used at
* binding time and returns a reference to a protocol-agnostic
- * base master port.
+ * port.
*
* @param if_name Port name
* @param idx Index in the case of a VectorPort
*
* @return A reference to the given port
*/
- BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
-
- /**
- * Get a slave port with a given name and index. This is used at
- * binding time and returns a reference to a protocol-agnostic
- * base master port.
- *
- * @param if_name Port name
- * @param idx Index in the case of a VectorPort
- *
- * @return A reference to the given port
- */
- BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
};
fatal("Address mapper is not connected on both sides.\n");
}
-BaseMasterPort&
-AddrMapper::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+AddrMapper::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master") {
return masterPort;
- } else {
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort&
-AddrMapper::getSlavePort(const std::string& if_name, PortID idx)
-{
- if (if_name == "slave") {
+ } else if (if_name == "slave") {
return slavePort;
} else {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
virtual ~AddrMapper() { }
- virtual BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
-
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
virtual void init();
{
}
-BaseMasterPort&
-Bridge::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+Bridge::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master")
return masterPort;
- else
- // pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
-}
-
-BaseSlavePort&
-Bridge::getSlavePort(const std::string &if_name, PortID idx)
-{
- if (if_name == "slave")
+ else if (if_name == "slave")
return slavePort;
else
// pass it along to our super class
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
public:
- virtual BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
virtual void init();
forwardSnoops = cpuSidePort.isSnooping();
}
-BaseMasterPort &
-BaseCache::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+BaseCache::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "mem_side") {
return memSidePort;
- } else {
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort &
-BaseCache::getSlavePort(const std::string &if_name, PortID idx)
-{
- if (if_name == "cpu_side") {
+ } else if (if_name == "cpu_side") {
return cpuSidePort;
- } else {
- return MemObject::getSlavePort(if_name, idx);
+ } else {
+ return MemObject::getPort(if_name, idx);
}
}
void init() override;
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
- BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/**
* Query block size of a cache.
ppPktResp.reset(new ProbePoints::Packet(getProbeManager(), "PktResponse"));
}
-BaseMasterPort&
-CommMonitor::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+CommMonitor::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master") {
return masterPort;
- } else {
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort&
-CommMonitor::getSlavePort(const std::string& if_name, PortID idx)
-{
- if (if_name == "slave") {
+ } else if (if_name == "slave") {
return slavePort;
} else {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
void regProbePoints() override;
public: // MemObject interfaces
- BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
-
- BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
private:
functionalAccess(pkt);
}
-BaseSlavePort&
-DRAMCtrl::getSlavePort(const string &if_name, PortID idx)
+Port &
+DRAMCtrl::getPort(const string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
} else {
return port;
}
DrainState drain() override;
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
virtual void init() override;
virtual void startup() override;
signalDrainDone();
}
-BaseSlavePort&
-DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+DRAMSim2::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
} else {
return port;
}
DrainState drain() override;
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void init() override;
void startup() override;
masterId(params->system->getMasterId(this))
{}
-BaseMasterPort &
-ExternalMaster::getMasterPort(const std::string &if_name,
- PortID idx)
+Port &
+ExternalMaster::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port") {
DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n",
}
return *externalPort;
} else {
- return MemObject::getMasterPort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
{
public:
/** Derive from this class to create an external port interface */
- class Port : public MasterPort
+ class ExternalPort : public MasterPort
{
protected:
ExternalMaster &owner;
public:
- Port(const std::string &name_,
+ ExternalPort(const std::string &name_,
ExternalMaster &owner_) :
MasterPort(name_, &owner_), owner(owner_)
{ }
- ~Port() { }
+ ~ExternalPort() { }
/** Any or all of recv... can be overloaded to provide the port's
* functionality */
public:
/** Create or find an external port which can be bound. Returns
* NULL on failure */
- virtual Port *getExternalPort(
+ virtual ExternalPort *getExternalPort(
const std::string &name, ExternalMaster &owner,
const std::string &port_data) = 0;
};
protected:
/** The peer port for the gem5 port "port" */
- Port *externalPort;
+ ExternalPort *externalPort;
/** Name of the bound port. This will be name() + ".port" */
std::string portName;
public:
ExternalMaster(ExternalMasterParams *params);
- /** MasterPort interface. Responds only to port "port" */
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ /** Port interface. Responds only to port "port" */
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/** Register a handler which can provide ports with port_type ==
* handler_name */
* a message. The stub port can be used to configure and test a system
* where the external port is used for a peripheral before connecting
* the external port */
-class StubSlavePort : public ExternalSlave::Port
+class StubSlavePort : public ExternalSlave::ExternalPort
{
public:
void processResponseEvent();
StubSlavePort(const std::string &name_,
ExternalSlave &owner_) :
- ExternalSlave::Port(name_, owner_),
+ ExternalSlave::ExternalPort(name_, owner_),
responseEvent([this]{ processResponseEvent(); }, name()),
responsePacket(NULL), mustRetry(false)
{ }
ExternalSlave::Handler
{
public:
- ExternalSlave::Port *getExternalPort(
+ ExternalSlave::ExternalPort *getExternalPort(
const std::string &name_,
ExternalSlave &owner,
const std::string &port_data)
ExternalSlave::portHandlers;
AddrRangeList
-ExternalSlave::Port::getAddrRanges() const
+ExternalSlave::ExternalPort::getAddrRanges() const
{
return owner.addrRanges;
}
registerHandler("stub", new StubSlavePortHandler);
}
-BaseSlavePort &
-ExternalSlave::getSlavePort(const std::string &if_name,
- PortID idx)
+Port &
+ExternalSlave::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "port") {
DPRINTF(ExternalPort, "Trying to bind external port: %s %s\n",
}
return *externalPort;
} else {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
{
public:
/** Derive from this class to create an external port interface */
- class Port : public SlavePort
+ class ExternalPort : public SlavePort
{
protected:
ExternalSlave &owner;
public:
- Port(const std::string &name_,
+ ExternalPort(const std::string &name_,
ExternalSlave &owner_) :
SlavePort(name_, &owner_), owner(owner_)
{ }
- ~Port() { }
+ ~ExternalPort() { }
/** Any or all of recv... can be overloaded to provide the port's
* functionality */
public:
/** Create or find an external port which can be bound. Returns
* NULL on failure */
- virtual Port *getExternalPort(
+ virtual ExternalPort *getExternalPort(
const std::string &name, ExternalSlave &owner,
const std::string &port_data) = 0;
};
protected:
/** The peer port for the gem5 port "port" */
- Port *externalPort;
+ ExternalPort *externalPort;
/** Name of the bound port. This will be name() + ".port" */
std::string portName;
public:
ExternalSlave(ExternalSlaveParams *params);
- /** SlavePort interface. Responds only to port "port" */
- BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID);
+ /** Port interface. Responds only to port "port" */
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/** Register a handler which can provide ports with port_type ==
* handler_name */
fatal("Communication monitor is not connected on both sides.\n");
}
-BaseMasterPort&
-MemCheckerMonitor::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+MemCheckerMonitor::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master" || if_name == "mem_side") {
return masterPort;
- } else {
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort&
-MemCheckerMonitor::getSlavePort(const std::string& if_name, PortID idx)
-{
- if (if_name == "slave" || if_name == "cpu_side") {
+ } else if (if_name == "slave" || if_name == "cpu_side") {
return slavePort;
} else {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
/** Destructor */
~MemCheckerMonitor();
- virtual BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
-
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
virtual void init();
}
-BaseMasterPort&
-MemDelay::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+MemDelay::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master") {
return masterPort;
- } else {
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort&
-MemDelay::getSlavePort(const std::string& if_name, PortID idx)
-{
- if (if_name == "slave") {
+ } else if (if_name == "slave") {
return slavePort;
} else {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
void init() override;
- protected: // Port interfaces
- BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
-
- BaseSlavePort& getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ protected: // Port interface
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
class MasterPort : public QueuedMasterPort
{
: ClockedObject(params)
{
}
-
-BaseMasterPort&
-MemObject::getMasterPort(const std::string& if_name, PortID idx)
-{
- fatal("%s does not have any master port named %s\n", name(), if_name);
-}
-
-BaseSlavePort&
-MemObject::getSlavePort(const std::string& if_name, PortID idx)
-{
- fatal("%s does not have any slave port named %s\n", name(), if_name);
-}
#include "sim/clocked_object.hh"
/**
- * The MemObject class extends the ClockedObject with accessor functions
- * to get its master and slave ports.
+ * The MemObject class extends the ClockedObject for historical reasons.
*/
class MemObject : public ClockedObject
{
{ return dynamic_cast<const Params *>(_params); }
MemObject(const Params *params);
-
- /**
- * Get a master port with a given name and index. This is used at
- * binding time and returns a reference to a protocol-agnostic
- * base master port.
- *
- * @param if_name Port name
- * @param idx Index in the case of a VectorPort
- *
- * @return A reference to the given port
- */
- virtual BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
-
- /**
- * Get a slave port with a given name and index. This is used at
- * binding time and returns a reference to a protocol-agnostic
- * base master port.
- *
- * @param if_name Port name
- * @param idx Index in the case of a VectorPort
- *
- * @return A reference to the given port
- */
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
};
#endif //__MEM_MEM_OBJECT_HH__
pkt->popLabel();
}
-BaseSlavePort &
-MemSinkCtrl::getSlavePort(const std::string &interface, PortID idx)
+Port &
+MemSinkCtrl::getPort(const std::string &interface, PortID idx)
{
if (interface != "port") {
- return MemObject::getSlavePort(interface, idx);
+ return MemObject::getPort(interface, idx);
} else {
return port;
}
/**
* Getter method to access this memory's slave port
*
- * @param interface interface name
+ * @param if_name interface name
* @param idx port ID number
* @return reference to this memory's slave port
*/
- BaseSlavePort& getSlavePort(const std::string&,
- PortID = InvalidPortID) override;
+ Port &getPort(const std::string &if_name, PortID=InvalidPortID) override;
/**
* Initializes this object
#include "base/trace.hh"
#include "debug/RubyQueue.hh"
+#include "mem/packet.hh"
+#include "mem/port.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
+#include "mem/ruby/network/dummy_port.hh"
#include "mem/ruby/slicc_interface/Message.hh"
-#include "mem/packet.hh"
#include "params/MessageBuffer.hh"
#include "sim/sim_object.hh"
void setIncomingLink(int link_id) { m_input_link_id = link_id; }
void setVnet(int net) { m_vnet_id = net; }
+ Port &
+ getPort(const std::string &, PortID idx=InvalidPortID) override
+ {
+ return RubyDummyPort::instance();
+ }
+
void regStats();
// Function for figuring out if any of the messages in the buffer need
#include "base/addr_range.hh"
#include "base/types.hh"
#include "mem/packet.hh"
+#include "mem/port.hh"
#include "mem/protocol/LinkDirection.hh"
#include "mem/protocol/MessageSizeType.hh"
#include "mem/ruby/common/MachineID.hh"
#include "mem/ruby/common/TypeDefines.hh"
#include "mem/ruby/network/Topology.hh"
+#include "mem/ruby/network/dummy_port.hh"
#include "params/RubyNetwork.hh"
#include "sim/clocked_object.hh"
*/
NodeID addressToNodeID(Addr addr, MachineType mtype);
+ Port &
+ getPort(const std::string &, PortID idx=InvalidPortID) override
+ {
+ return RubyDummyPort::instance();
+ }
+
protected:
// Private copy constructor and assignment operator
Network(const Network& obj);
--- /dev/null
+/*
+ * Copyright 2019 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __MEM_RUBY_NETWORK_DUMMY_PORT_HH__
+#define __MEM_RUBY_NETWORK_DUMMY_PORT_HH__
+
+#include "mem/port.hh"
+
+class RubyDummyPort : public Port
+{
+ public:
+ RubyDummyPort() : Port("DummyPort", -1) {}
+
+ void
+ bind(Port &peer) override
+ {
+ // No need to connect anything here currently. MessageBuffer
+ // port connections only serve to print the connections in
+ // the config output.
+ // TODO: Add real ports to MessageBuffers and use MemObject connect
+ // code below to bind MessageBuffer senders and receivers
+ }
+ void unbind() override {}
+
+ static RubyDummyPort &
+ instance()
+ {
+ static RubyDummyPort dummy;
+ return dummy;
+ }
+};
+
+#endif //__MEM_RUBY_NETWORK_DUMMY_PORT_HH__
return (m_block_map.count(addr) > 0);
}
-BaseMasterPort &
-AbstractController::getMasterPort(const std::string &if_name,
- PortID idx)
+Port &
+AbstractController::getPort(const std::string &if_name, PortID idx)
{
return memoryPort;
}
virtual void initNetQueues() = 0;
/** A function used to return the port associated with this bus object. */
- BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID);
void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
}
-BaseMasterPort &
-RubyPort::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+RubyPort::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "mem_master_port") {
return memMasterPort;
- }
-
- if (if_name == "pio_master_port") {
+ } else if (if_name == "pio_master_port") {
return pioMasterPort;
- }
-
- // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
- // port
- if (if_name != "master") {
- // pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
- } else {
+ } else if (if_name == "mem_slave_port") {
+ return memSlavePort;
+ } else if (if_name == "pio_slave_port") {
+ return pioSlavePort;
+ } else if (if_name == "master") {
+ // used by the x86 CPUs to connect the interrupt PIO and interrupt
+ // slave port
if (idx >= static_cast<PortID>(master_ports.size())) {
- panic("RubyPort::getMasterPort: unknown index %d\n", idx);
+ panic("RubyPort::getPort master: unknown index %d\n", idx);
}
return *master_ports[idx];
- }
-}
-
-BaseSlavePort &
-RubyPort::getSlavePort(const std::string &if_name, PortID idx)
-{
- if (if_name == "mem_slave_port") {
- return memSlavePort;
- }
-
- if (if_name == "pio_slave_port")
- return pioSlavePort;
-
- // used by the CPUs to connect the caches to the interconnect, and
- // for the x86 case also the interrupt master
- if (if_name != "slave") {
- // pass it along to our super class
- return MemObject::getSlavePort(if_name, idx);
- } else {
+ } else if (if_name == "slave") {
+ // used by the CPUs to connect the caches to the interconnect, and
+ // for the x86 case also the interrupt master
if (idx >= static_cast<PortID>(slave_ports.size())) {
- panic("RubyPort::getSlavePort: unknown index %d\n", idx);
+ panic("RubyPort::getPort slave: unknown index %d\n", idx);
}
return *slave_ports[idx];
}
+
+ // pass it along to our super class
+ return MemObject::getPort(if_name, idx);
}
RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
void init() override;
- BaseMasterPort &getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
- BaseSlavePort &getSlavePort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
virtual int outstandingCount() const = 0;
{
}
-BaseMasterPort&
-SerialLink::getMasterPort(const std::string &if_name, PortID idx)
+Port&
+SerialLink::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master")
return masterPort;
- else
- // pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
-}
-
-BaseSlavePort&
-SerialLink::getSlavePort(const std::string &if_name, PortID idx)
-{
- if (if_name == "slave")
+ else if (if_name == "slave")
return slavePort;
else
// pass it along to our super class
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
public:
- virtual BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
- virtual BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID);
virtual void init();
dequeue();
}
-BaseSlavePort &
-SimpleMemory::getSlavePort(const std::string &if_name, PortID idx)
+Port &
+SimpleMemory::getPort(const std::string &if_name, PortID idx)
{
if (if_name != "port") {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
} else {
return port;
}
DrainState drain() override;
- BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
void init() override;
protected:
{
}
-BaseMasterPort &
-BaseXBar::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+BaseXBar::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master" && idx < masterPorts.size()) {
// the master port index translates directly to the vector position
return *masterPorts[idx];
} else if (if_name == "default") {
return *masterPorts[defaultPortID];
- } else {
- return MemObject::getMasterPort(if_name, idx);
- }
-}
-
-BaseSlavePort &
-BaseXBar::getSlavePort(const std::string &if_name, PortID idx)
-{
- if (if_name == "slave" && idx < slavePorts.size()) {
+ } else if (if_name == "slave" && idx < slavePorts.size()) {
// the slave port index translates directly to the vector position
return *slavePorts[idx];
} else {
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
}
virtual void init();
/** A function used to return the port associated with this object. */
- BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
- BaseSlavePort& getSlavePort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
virtual void regStats();
Source('pybind11/core.cc', add_tags='python')
Source('pybind11/debug.cc', add_tags='python')
Source('pybind11/event.cc', add_tags='python')
-Source('pybind11/pyobject.cc', add_tags='python')
Source('pybind11/stats.cc', add_tags='python')
void pybind_init_debug(pybind11::module &m_native);
void pybind_init_event(pybind11::module &m_native);
-void pybind_init_pyobject(pybind11::module &m_native);
void pybind_init_stats(pybind11::module &m_native);
#endif
+++ /dev/null
-/*
- * Copyright (c) 2017 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#include "pybind11/pybind11.h"
-
-#include <string>
-
-#include "config/the_isa.hh"
-
-#include "dev/net/etherdevice.hh"
-#include "dev/net/etherint.hh"
-#include "dev/net/etherobject.hh"
-#include "mem/mem_object.hh"
-#include "mem/ruby/network/Network.hh"
-#include "mem/ruby/slicc_interface/AbstractController.hh"
-#include "mem/ruby/system/Sequencer.hh"
-#include "sim/full_system.hh"
-
-namespace py = pybind11;
-
-/**
- * Connect the described MemObject ports. Called from Python.
- * The indices i1 & i2 will be -1 for regular ports, >= 0 for vector ports.
- * SimObject1 is the master, and SimObject2 is the slave
- */
-static int
-connectPorts(SimObject *o1, const std::string &name1, int i1,
- SimObject *o2, const std::string &name2, int i2)
-{
- auto *eo1 = dynamic_cast<EtherObject*>(o1);
- auto *eo2 = dynamic_cast<EtherObject*>(o2);
-
- if (eo1 && eo2) {
- EtherInt *p1 = eo1->getEthPort(name1, i1);
- EtherInt *p2 = eo2->getEthPort(name2, i2);
-
- if (p1 && p2) {
- p1->setPeer(p2);
- p2->setPeer(p1);
-
- return 1;
- }
- }
-
- // These could be MessageBuffers from the ruby memory system. If so, they
- // need not be connected to anything currently.
- MessageBuffer *mb1, *mb2;
- mb1 = dynamic_cast<MessageBuffer*>(o1);
- mb2 = dynamic_cast<MessageBuffer*>(o2);
- Network *nw1, *nw2;
- nw1 = dynamic_cast<Network*>(o1);
- nw2 = dynamic_cast<Network*>(o2);
-
- if ((mb1 || nw1) && (mb2 || nw2)) {
- // No need to connect anything here currently. MessageBuffer
- // connections in Python only serve to print the connections in
- // the config output.
- // TODO: Add real ports to MessageBuffers and use MemObject connect
- // code below to bind MessageBuffer senders and receivers
- return 1;
- }
-
- MemObject *mo1, *mo2;
- mo1 = dynamic_cast<MemObject*>(o1);
- mo2 = dynamic_cast<MemObject*>(o2);
-
- if (mo1 == NULL || mo2 == NULL) {
- panic ("Error casting SimObjects %s and %s to MemObject", o1->name(),
- o2->name());
- }
-
- // generic master/slave port connection
- BaseMasterPort& masterPort = mo1->getMasterPort(name1, i1);
- BaseSlavePort& slavePort = mo2->getSlavePort(name2, i2);
-
- masterPort.bind(slavePort);
-
- return 1;
-}
-
-void
-pybind_init_pyobject(py::module &m_native)
-{
- py::module m = m_native.def_submodule("pyobject");
-
- m.def("connectPorts", &connectPorts);
-}
Source('init_signals.cc')
Source('main.cc', tags='main')
Source('port.cc')
+Source('python.cc', add_tags='python')
Source('root.cc')
Source('serialize.cc')
Source('drain.cc')
* getCxxConfigDirectoryEntry for each object. */
/* It would be nice to be able to catch the errors from these calls. */
- BaseMasterPort &master_port = master_mem_object->getMasterPort(
+ Port &master_port = master_mem_object->getPort(
master_port_name, master_port_index);
- BaseSlavePort &slave_port = slave_mem_object->getSlavePort(
+ Port &slave_port = slave_mem_object->getPort(
slave_port_name, slave_port_index);
if (master_port.isConnected()) {
pybind_init_debug(m_m5);
pybind_init_event(m_m5);
- pybind_init_pyobject(m_m5);
pybind_init_stats(m_m5);
for (auto &kv : getMap()) {
--- /dev/null
+/*
+ * Copyright 2019 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "pybind11/pybind11.h"
+#include "sim/init.hh"
+#include "sim/port.hh"
+
+namespace
+{
+
+void
+sim_pybind(pybind11::module &m_internal)
+{
+ pybind11::module m = m_internal.def_submodule("sim");
+ pybind11::class_<
+ Port, std::unique_ptr<Port, pybind11::nodelete>>(m, "Port")
+ .def("bind", &Port::bind)
+ ;
+}
+EmbeddedPyBind embed_("sim", &sim_pybind);
+
+} // anonymous namespace
panic("System port on %s is not connected.\n", name());
}
-BaseMasterPort&
-System::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+System::getPort(const std::string &if_name, PortID idx)
{
// no need to distinguish at the moment (besides checking)
return _systemPort;
/**
* Additional function to return the Port of a memory object.
*/
- BaseMasterPort& getMasterPort(const std::string &if_name,
- PortID idx = InvalidPortID) override;
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID) override;
/** @{ */
/**
projects / gem5.git / commitdiff