(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index e94681854be4b060f1b3ab7dbf7c4c577fca51fc..1ae1e76040a6ca275ab52bdcd596c5529f101b97 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -13,6 +13,8 @@ as a concept became popular.
    just because it is prefixed (semantic caveats below)
 3. A hardware-level for-loop (the prefix) makes vector elements
    100% synonymous with scalar instructions (the suffix)
+4. Exactly as with Scalar RISC ISAs, the uniformity does produce
+   "holes" in the encoding or some strange combinations.
 
 How can a Vector ISA even exist when no actual Vector instructions
 are permitted to be added? It comes down to the strict RISC abstraction.