This patch is adding new SVE2 instructions added to support SME extension.
The following SVE2 instructions are added by the SME architecture:
* PSEL,
* REVD, SCLAMP and UCLAMP.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_pred_reg_with_index):
New parser.
(parse_operands): New parser.
* testsuite/gas/aarch64/sme-9-illegal.d: New test.
* testsuite/gas/aarch64/sme-9-illegal.l: New test.
* testsuite/gas/aarch64/sme-9-illegal.s: New test.
* testsuite/gas/aarch64/sme-9.d: New test.
* testsuite/gas/aarch64/sme-9.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_PnT_Wm_imm.
opcodes/ChangeLog:
* aarch64-asm.c (aarch64_ins_sme_pred_reg_with_index):
New inserter.
* aarch64-dis.c (aarch64_ext_sme_pred_reg_with_index):
New extractor.
* aarch64-opc.c (aarch64_print_operand): Printout of
OPND_SME_PnT_Wm_imm.
* aarch64-opc.h (enum aarch64_field_kind): New bitfields
FLD_SME_Rm, FLD_SME_i1, FLD_SME_tszh, FLD_SME_tszl.
* aarch64-tbl.h (OP_SVE_NN_BHSD): New qualifier.
(OP_SVE_QMQ): New qualifier.
(struct aarch64_opcode): New instructions PSEL, REVD,
SCLAMP and UCLAMP.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
return TOLOWER (p[0]);
}
+/* Parse the name of the source scalable predicate register, the index base
+ register W12-W15 and the element index. Function performs element index
+ limit checks as well as qualifier type checks.
+
+ <Pn>.<T>[<Wv>, <imm>]
+ <Pn>.<T>[<Wv>, #<imm>]
+
+ On success function sets <Wv> to INDEX_BASE_REG, <T> to QUALIFIER and
+ <imm> to IMM.
+ Function returns <Pn>, or PARSE_FAIL.
+*/
+static int
+parse_sme_pred_reg_with_index(char **str,
+ int *index_base_reg,
+ int *imm,
+ aarch64_opnd_qualifier_t *qualifier)
+{
+ int regno;
+ int64_t imm_limit;
+ int64_t imm_value;
+ const reg_entry *reg = parse_reg_with_qual (str, REG_TYPE_PN, qualifier);
+
+ if (reg == NULL)
+ return PARSE_FAIL;
+ regno = reg->number;
+
+ switch (*qualifier)
+ {
+ case AARCH64_OPND_QLF_S_B:
+ imm_limit = 15;
+ break;
+ case AARCH64_OPND_QLF_S_H:
+ imm_limit = 7;
+ break;
+ case AARCH64_OPND_QLF_S_S:
+ imm_limit = 3;
+ break;
+ case AARCH64_OPND_QLF_S_D:
+ imm_limit = 1;
+ break;
+ default:
+ set_syntax_error (_("wrong predicate register element size, allowed b, h, s and d"));
+ return PARSE_FAIL;
+ }
+
+ if (! parse_sme_za_hv_tiles_operand_index (str, index_base_reg, &imm_value))
+ return PARSE_FAIL;
+
+ if (imm_value < 0 || imm_value > imm_limit)
+ {
+ set_syntax_error (_("element index out of range for given variant"));
+ return PARSE_FAIL;
+ }
+
+ *imm = imm_value;
+
+ return regno;
+}
+
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL.
info->reg.regno = val;
break;
+ case AARCH64_OPND_SME_PnT_Wm_imm:
+ /* <Pn>.<T>[<Wm>, #<imm>] */
+ {
+ int index_base_reg;
+ int imm;
+ val = parse_sme_pred_reg_with_index (&str,
+ &index_base_reg,
+ &imm,
+ &qualifier);
+ if (val == PARSE_FAIL)
+ goto failure;
+
+ info->za_tile_vector.regno = val;
+ info->za_tile_vector.index.regno = index_base_reg;
+ info->za_tile_vector.index.imm = imm;
+ info->qualifier = qualifier;
+ break;
+ }
+
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
case AARCH64_OPND_SVE_ADDR_RI_S4x32:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme-9-illegal.s
+#error_output: sme-9-illegal.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: wrong predicate register element size, allowed b, h, s and d at operand 3 -- `psel p1,p15,p3.q\[w15\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p1,p15,p3.b\[w11\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p8,p11,p15.h\[w16\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p2,p7,p15.s\[w3\]'
+[^:]*:[0-9]+: Error: expected vector select register W12-W15 at operand 3 -- `psel p13,p3,p1.d\[w17\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p5,p12,p9.b\[w15,#16\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]'
+[^:]*:[0-9]+: Error: element index out of range for given variant at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]'
+[^:]*:[0-9]+: Error: operand mismatch -- `revd z0.q,p0/m,z0.b'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: revd z0.q, p0/m, z0.q
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z8.b,z1.b,z31.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sclamp z8.b, z1.b, z31.b
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: sclamp z8.h, z1.h, z31.h
+[^:]*:[0-9]+: Info: sclamp z8.s, z1.s, z31.s
+[^:]*:[0-9]+: Info: sclamp z8.d, z1.d, z31.d
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.h,z0.h,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: sclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info: sclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Info: sclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z0.s,z31.s,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sclamp z0.s, z31.s, z17.s
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: sclamp z0.b, z31.b, z17.b
+[^:]*:[0-9]+: Info: sclamp z0.h, z31.h, z17.h
+[^:]*:[0-9]+: Info: sclamp z0.d, z31.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.d,z0.d,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: sclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info: sclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info: sclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Error: operand mismatch -- `sclamp z31.q,z0.d,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: sclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: sclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info: sclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info: sclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z8.b,z1.b,z31.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: uclamp z8.b, z1.b, z31.b
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: uclamp z8.h, z1.h, z31.h
+[^:]*:[0-9]+: Info: uclamp z8.s, z1.s, z31.s
+[^:]*:[0-9]+: Info: uclamp z8.d, z1.d, z31.d
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.h,z0.h,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: uclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: uclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info: uclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Info: uclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z0.s,z31.s,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: uclamp z0.s, z31.s, z17.s
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: uclamp z0.b, z31.b, z17.b
+[^:]*:[0-9]+: Info: uclamp z0.h, z31.h, z17.h
+[^:]*:[0-9]+: Info: uclamp z0.d, z31.d, z17.d
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.d,z0.d,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: uclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: uclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info: uclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info: uclamp z31.s, z0.s, z17.s
+[^:]*:[0-9]+: Error: operand mismatch -- `uclamp z31.q,z0.d,z17.q'
+[^:]*:[0-9]+: Info: did you mean this\?
+[^:]*:[0-9]+: Info: uclamp z31.d, z0.d, z17.d
+[^:]*:[0-9]+: Info: other valid variant\(s\):
+[^:]*:[0-9]+: Info: uclamp z31.b, z0.b, z17.b
+[^:]*:[0-9]+: Info: uclamp z31.h, z0.h, z17.h
+[^:]*:[0-9]+: Info: uclamp z31.s, z0.s, z17.s
--- /dev/null
+/* Scalable Matrix Extension (SME). */
+
+psel p1, p15, p3.q[w15]
+psel p1, p15, p3.b[w11]
+psel p8, p11, p15.h[w16]
+psel p2, p7, p15.s[w3]
+psel p13, p3, p1.d[w17]
+psel p5, p12, p9.b[w15, #16]
+psel p1, p8, p6.h[w14, #8]
+psel p8, p4, p15.s[w13, #4]
+psel p1, p1, p1.d[w12, #2]
+
+revd z0.q, p0/m, z0.b
+
+sclamp z8.b, z1.b, z31.q
+sclamp z31.h, z0.h, z17.q
+sclamp z0.s, z31.s, z17.q
+sclamp z31.d, z0.d, z17.q
+sclamp z31.q, z0.d, z17.q
+
+uclamp z8.b, z1.b, z31.q
+uclamp z31.h, z0.h, z17.q
+uclamp z0.s, z31.s, z17.q
+uclamp z31.d, z0.d, z17.q
+uclamp z31.q, z0.d, z17.q
--- /dev/null
+#name: SVE2 instructions added to support SME
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: 25277c61 psel p1, p15, p3.b\[w15, 0\]
+ 4: 252778a2 psel p2, p14, p5.b\[w15, 0\]
+ 8: 257f74e3 psel p3, p13, p7.b\[w15, 7\]
+ c: 25ff7125 psel p5, p12, p9.b\[w15, 15\]
+ 10: 252a6de8 psel p8, p11, p15.h\[w14, 0\]
+ 14: 252a682d psel p13, p10, p1.h\[w14, 0\]
+ 18: 257a640f psel p15, p9, p0.h\[w14, 3\]
+ 1c: 25fa60c1 psel p1, p8, p6.h\[w14, 7\]
+ 20: 25315de2 psel p2, p7, p15.s\[w13, 0\]
+ 24: 253159e3 psel p3, p6, p15.s\[w13, 0\]
+ 28: 257155e5 psel p5, p5, p15.s\[w13, 1\]
+ 2c: 25f151e8 psel p8, p4, p15.s\[w13, 3\]
+ 30: 25604c2d psel p13, p3, p1.d\[w12, 0\]
+ 34: 2560482f psel p15, p2, p1.d\[w12, 0\]
+ 38: 25e04421 psel p1, p1, p1.d\[w12, 1\]
+ 3c: 052e8000 revd z0.q, p0/m, z0.q
+ 40: 052e9c00 revd z0.q, p7/m, z0.q
+ 44: 052e83e0 revd z0.q, p0/m, z31.q
+ 48: 052e9c1f revd z31.q, p7/m, z0.q
+ 4c: 4411c3e0 sclamp z0.b, z31.b, z17.b
+ 50: 4411c01f sclamp z31.b, z0.b, z17.b
+ 54: 441fc028 sclamp z8.b, z1.b, z31.b
+ 58: 4451c01f sclamp z31.h, z0.h, z17.h
+ 5c: 445fc028 sclamp z8.h, z1.h, z31.h
+ 60: 4491c3e0 sclamp z0.s, z31.s, z17.s
+ 64: 4491c01f sclamp z31.s, z0.s, z17.s
+ 68: 449fc028 sclamp z8.s, z1.s, z31.s
+ 6c: 44d1c3e0 sclamp z0.d, z31.d, z17.d
+ 70: 44d1c01f sclamp z31.d, z0.d, z17.d
+ 74: 44dfc028 sclamp z8.d, z1.d, z31.d
+ 78: 4411c7e0 uclamp z0.b, z31.b, z17.b
+ 7c: 4411c41f uclamp z31.b, z0.b, z17.b
+ 80: 441fc428 uclamp z8.b, z1.b, z31.b
+ 84: 4451c7e0 uclamp z0.h, z31.h, z17.h
+ 88: 4451c41f uclamp z31.h, z0.h, z17.h
+ 8c: 445fc428 uclamp z8.h, z1.h, z31.h
+ 90: 4491c7e0 uclamp z0.s, z31.s, z17.s
+ 94: 4491c41f uclamp z31.s, z0.s, z17.s
+ 98: 449fc428 uclamp z8.s, z1.s, z31.s
+ 9c: 44d1c7e0 uclamp z0.d, z31.d, z17.d
+ a0: 44d1c41f uclamp z31.d, z0.d, z17.d
+ a4: 44dfc428 uclamp z8.d, z1.d, z31.d
+ a8: 0420bca3 movprfx z3, z5
+ ac: 052e84a3 revd z3.q, p1/m, z5.q
+ b0: 0420bc81 movprfx z1, z4
+ b4: 052e84a1 revd z1.q, p1/m, z5.q
+ b8: 0420bc81 movprfx z1, z4
+ bc: 440bc141 sclamp z1.b, z10.b, z11.b
+ c0: 0420bc82 movprfx z2, z4
+ c4: 444bc142 sclamp z2.h, z10.h, z11.h
+ c8: 0420bc83 movprfx z3, z4
+ cc: 448bc143 sclamp z3.s, z10.s, z11.s
+ d0: 0420bca4 movprfx z4, z5
+ d4: 44cbc144 sclamp z4.d, z10.d, z11.d
+ d8: 0420bc81 movprfx z1, z4
+ dc: 440bc541 uclamp z1.b, z10.b, z11.b
+ e0: 0420bc82 movprfx z2, z4
+ e4: 444bc542 uclamp z2.h, z10.h, z11.h
+ e8: 0420bc83 movprfx z3, z4
+ ec: 448bc543 uclamp z3.s, z10.s, z11.s
+ f0: 0420bca4 movprfx z4, z5
+ f4: 44cbc544 uclamp z4.d, z10.d, z11.d
+ f8: 25277c61 psel p1, p15, p3.b\[w15, 0\]
+ fc: 252778a2 psel p2, p14, p5.b\[w15, 0\]
--- /dev/null
+/* SVE2 instructions added to support SME. */
+
+psel p1, p15, p3.b[w15, 0]
+psel p2, p14, p5.b[w15, 0]
+psel p3, p13, p7.b[w15, 7]
+psel p5, p12, p9.b[w15, 15]
+
+psel p8, p11, p15.h[w14, 0]
+psel p13, p10, p1.h[w14, 0]
+psel p15, p9, p0.h[w14, 3]
+psel p1, p8, p6.h[w14, 7]
+
+psel p2, p7, p15.s[w13, 0]
+psel p3, p6, p15.s[w13, 0]
+psel p5, p5, p15.s[w13, 1]
+psel p8, p4, p15.s[w13, 3]
+
+psel p13, p3, p1.d[w12, 0]
+psel p15, p2, p1.d[w12, 0]
+psel p1, p1, p1.d[w12, 1]
+
+revd z0.q, p0/m, z0.q
+revd z0.q, p7/m, z0.q
+revd z0.q, p0/m, z31.q
+revd z31.q, p7/m, z0.q
+
+sclamp z0.b, z31.b, z17.b
+sclamp z31.b, z0.b, z17.b
+sclamp z8.b, z1.b, z31.b
+sclamp z31.h, z0.h, z17.h
+sclamp z8.h, z1.h, z31.h
+sclamp z0.s, z31.s, z17.s
+sclamp z31.s, z0.s, z17.s
+sclamp z8.s, z1.s, z31.s
+sclamp z0.d, z31.d, z17.d
+sclamp z31.d, z0.d, z17.d
+sclamp z8.d, z1.d, z31.d
+
+uclamp z0.b, z31.b, z17.b
+uclamp z31.b, z0.b, z17.b
+uclamp z8.b, z1.b, z31.b
+uclamp z0.h, z31.h, z17.h
+uclamp z31.h, z0.h, z17.h
+uclamp z8.h, z1.h, z31.h
+uclamp z0.s, z31.s, z17.s
+uclamp z31.s, z0.s, z17.s
+uclamp z8.s, z1.s, z31.s
+uclamp z0.d, z31.d, z17.d
+uclamp z31.d, z0.d, z17.d
+uclamp z8.d, z1.d, z31.d
+
+/* The unpredicated MOVPRFX instruction. */
+movprfx z3, z5
+revd z3.q, p1/m, z5.q
+
+movprfx z1, z4
+revd z1.q, p1/m, z5.q
+
+movprfx z1, z4
+sclamp z1.b, z10.b, z11.b
+
+movprfx z2, z4
+sclamp z2.h, z10.h, z11.h
+
+movprfx z3, z4
+sclamp z3.s, z10.s, z11.s
+
+movprfx z4, z5
+sclamp z4.d, z10.d, z11.d
+
+movprfx z1, z4
+uclamp z1.b, z10.b, z11.b
+
+movprfx z2, z4
+uclamp z2.h, z10.h, z11.h
+
+movprfx z3, z4
+uclamp z3.s, z10.s, z11.s
+
+movprfx z4, z5
+uclamp z4.d, z10.d, z11.d
+
+foo .req p1
+bar .req w15
+psel foo, p15, p3.b[w15, 0]
+psel p2, p14, p5.b[bar, 0]
AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
+ AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
};
case 33:
case 34:
case 35:
- case 221:
+ case 222:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 189:
case 190:
case 215:
- case 220:
+ case 221:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 219:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 220:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
default: assert (0); abort ();
}
}
return true;
}
+/* Encode source scalable predicate register (Pn), name of the index base
+ register W12-W15 (Rm), and optional element index, defaulting to 0, in the
+ range 0 to one less than the number of vector elements in a 128-bit vector
+ register, encoded in "i1:tszh:tszl".
+*/
+bool
+aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int fld_pn = info->za_tile_vector.regno;
+ int fld_rm = info->za_tile_vector.index.regno - 12;
+ int imm = info->za_tile_vector.index.imm;
+ int fld_i1, fld_tszh, fld_tshl;
+
+ insert_field (self->fields[0], code, fld_rm, 0);
+ insert_field (self->fields[1], code, fld_pn, 0);
+
+ /* Optional element index, defaulting to 0, in the range 0 to one less than
+ the number of vector elements in a 128-bit vector register, encoded in
+ "i1:tszh:tszl".
+
+ i1 tszh tszl <T>
+ 0 0 000 RESERVED
+ x x xx1 B
+ x x x10 H
+ x x 100 S
+ x 1 000 D
+ */
+ switch (info->qualifier)
+ {
+ case AARCH64_OPND_QLF_S_B:
+ /* <imm> is 4 bit value. */
+ fld_i1 = (imm >> 3) & 0x1;
+ fld_tszh = (imm >> 2) & 0x1;
+ fld_tshl = ((imm << 1) | 0x1) & 0x7;
+ break;
+ case AARCH64_OPND_QLF_S_H:
+ /* <imm> is 3 bit value. */
+ fld_i1 = (imm >> 2) & 0x1;
+ fld_tszh = (imm >> 1) & 0x1;
+ fld_tshl = ((imm << 2) | 0x2) & 0x7;
+ break;
+ case AARCH64_OPND_QLF_S_S:
+ /* <imm> is 2 bit value. */
+ fld_i1 = (imm >> 1) & 0x1;
+ fld_tszh = imm & 0x1;
+ fld_tshl = 0x4;
+ break;
+ case AARCH64_OPND_QLF_S_D:
+ /* <imm> is 1 bit value. */
+ fld_i1 = imm & 0x1;
+ fld_tszh = 0x1;
+ fld_tshl = 0x0;
+ break;
+ default:
+ assert (0);
+ }
+
+ insert_field (self->fields[2], code, fld_i1, 0);
+ insert_field (self->fields[3], code, fld_tszh, 0);
+ insert_field (self->fields[4], code, fld_tshl, 0);
+ return true;
+}
+
/* Miscellaneous encoding functions. */
/* Encode size[0], i.e. bit 22, for
AARCH64_DECL_OPD_INSERTER (ins_sme_za_array);
AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl);
AARCH64_DECL_OPD_INSERTER (ins_sme_sm_za);
+AARCH64_DECL_OPD_INSERTER (ins_sme_pred_reg_with_index);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2447;
+ return 2451;
}
else
{
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2455;
+ return 2459;
}
}
else
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2451;
+ return 2455;
}
else
{
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2458;
+ return 2462;
}
}
}
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2448;
+ return 2452;
}
else
{
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2456;
+ return 2460;
}
}
else
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2452;
+ return 2456;
}
else
{
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2459;
+ return 2463;
}
}
}
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2450;
+ return 2454;
}
else
{
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2457;
+ return 2461;
}
}
else
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2454;
+ return 2458;
}
}
else
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2449;
+ return 2453;
}
else
{
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2453;
+ return 2457;
}
}
}
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2445;
+ return 2449;
}
else
{
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2446;
+ return 2450;
}
}
else
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2444;
+ return 2448;
}
else
{
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2464;
+ return 2468;
}
}
}
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2465;
+ return 2469;
}
}
}
{
if (((word >> 21) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10001x0000xxxxx110xxxxxxxxxxxxx
- ldnt1b. */
- return 2104;
+ 010001x0xx0xxxxx110xx0xxxxxxxxxx
+ sclamp. */
+ return 2408;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10001x0100xxxxx110xxxxxxxxxxxxx
- ldnt1h. */
- return 2107;
+ 010001x0xx0xxxxx110xx1xxxxxxxxxx
+ uclamp. */
+ return 2409;
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x0010xxxxx110xxxxxxxxxxxxx
- ld1b. */
- return 1521;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0000xxxxx110xxxxxxxxxxxxx
+ ldnt1b. */
+ return 2104;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0100xxxxx110xxxxxxxxxxxxx
+ ldnt1h. */
+ return 2107;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x0110xxxxx110xxxxxxxxxxxxx
- ld1h. */
- return 1542;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0010xxxxx110xxxxxxxxxxxxx
+ ld1b. */
+ return 1521;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 110001x0110xxxxx110xxxxxxxxxxxxx
+ ld1h. */
+ return 1542;
+ }
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx011110xxxxxxxxxx
usdot. */
- return 2463;
+ return 2467;
}
}
}
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2492;
+ return 2496;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxxx00xxxxxxxxxxxxx
ld1rob. */
- return 2468;
+ return 2472;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxxx00xxxxxxxxxxxxx
ld1roh. */
- return 2469;
+ return 2473;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2489;
+ return 2493;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2496;
+ return 2500;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2495;
+ return 2499;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2488;
+ return 2492;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2494;
+ return 2498;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2493;
+ return 2497;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxx001xxxxxxxxxxxxx
ld1rob. */
- return 2472;
+ return 2476;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxx001xxxxxxxxxxxxx
ld1roh. */
- return 2473;
+ return 2477;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2466;
+ return 2470;
}
else
{
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2490;
+ return 2494;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2467;
+ return 2471;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000x00xxxxxxxxxx
zip1. */
- return 2476;
+ return 2480;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx
uzp1. */
- return 2478;
+ return 2482;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000110xxxxxxxxxx
trn1. */
- return 2480;
+ return 2484;
}
}
}
10987654321098765432109876543210
000001x1101xxxxx000x01xxxxxxxxxx
zip2. */
- return 2477;
+ return 2481;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx
uzp2. */
- return 2479;
+ return 2483;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000111xxxxxxxxxx
trn2. */
- return 2481;
+ return 2485;
}
}
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xx110100xxxxxxxxxxxxx
- revw. */
- return 1820;
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0110100xxxxxxxxxxxxx
+ revw. */
+ return 1820;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x1110100xxxxxxxxxxxxx
+ revd. */
+ return 2407;
+ }
}
}
}
10987654321098765432109876543210
010001x1000xxxxx100110xxxxxxxxxx
smmla. */
- return 2460;
+ return 2464;
}
else
{
10987654321098765432109876543210
010001x1100xxxxx100110xxxxxxxxxx
usmmla. */
- return 2462;
+ return 2466;
}
}
else
10987654321098765432109876543210
010001x1x10xxxxx100110xxxxxxxxxx
ummla. */
- return 2461;
+ return 2465;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx000xxxxxxxxxxxxx
ld1row. */
- return 2470;
+ return 2474;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx000xxxxxxxxxxxxx
ld1rod. */
- return 2471;
+ return 2475;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx001xxxxxxxxxxxxx
ld1row. */
- return 2474;
+ return 2478;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx001xxxxxxxxxxxxx
ld1rod. */
- return 2475;
+ return 2479;
}
}
}
}
else
{
- if (((word >> 13) & 0x1) == 0)
+ if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
- {
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1001xxxxx010xxxxxxxxxxxxx
- ld1sh. */
- return 1587;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1101xxxxx010xxxxxxxxxxxxx
- ld1sb. */
- return 1575;
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1011xxxxx010xxxxxxxxxxxxx
- ld1w. */
- return 1606;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1111xxxxx010xxxxxxxxxxxxx
- ld1d. */
- return 1528;
- }
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01xxxxxxxxxxxxxx
+ psel. */
+ return 2410;
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1001xxxxx011xxxxxxxxxxxxx
- ldff1sh. */
- return 1688;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1001xxxxx010xxxxxxxxxxxxx
+ ld1sh. */
+ return 1587;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1101xxxxx010xxxxxxxxxxxxx
+ ld1sb. */
+ return 1575;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1101xxxxx011xxxxxxxxxxxxx
- ldff1sb. */
- return 1676;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1011xxxxx010xxxxxxxxxxxxx
+ ld1w. */
+ return 1606;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1111xxxxx010xxxxxxxxxxxxx
+ ld1d. */
+ return 1528;
+ }
}
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1011xxxxx011xxxxxxxxxxxxx
- ldff1w. */
- return 1707;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1001xxxxx011xxxxxxxxxxxxx
+ ldff1sh. */
+ return 1688;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1101xxxxx011xxxxxxxxxxxxx
+ ldff1sb. */
+ return 1676;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x01001x1111xxxxx011xxxxxxxxxxxxx
- ldff1d. */
- return 1652;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1011xxxxx011xxxxxxxxxxxxx
+ ldff1w. */
+ return 1707;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 101001x1111xxxxx011xxxxxxxxxxxxx
+ ldff1d. */
+ return 1652;
+ }
}
}
}
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2491;
+ return 2495;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1001xxxxxxxxxx
smmla. */
- return 2482;
+ return 2486;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0101xxxxxxxxxx
sdot. */
- return 2408;
+ return 2412;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1011xxxxxxxxxx
usmmla. */
- return 2484;
+ return 2488;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0111xxxxxxxxxx
usdot. */
- return 2485;
+ return 2489;
}
}
else
10987654321098765432109876543210
1x001110000xxxxxxxxxxxxxxxxxxxxx
eor3. */
- return 2415;
+ return 2419;
}
else
{
10987654321098765432109876543210
1x001110100xxxxxxxxxxxxxxxxxxxxx
xar. */
- return 2417;
+ return 2421;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx0xxxxxxxxxxxxxxx
sm3ss1. */
- return 2419;
+ return 2423;
}
else
{
10987654321098765432109876543210
1x001110010xxxxx1xxx00xxxxxxxxxx
sm3tt1a. */
- return 2420;
+ return 2424;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx00xxxxxxxxxx
sha512su0. */
- return 2413;
+ return 2417;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx10xxxxxxxxxx
sm3tt2a. */
- return 2422;
+ return 2426;
}
}
else
10987654321098765432109876543210
1x001110010xxxxx1xxx01xxxxxxxxxx
sm3tt1b. */
- return 2421;
+ return 2425;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx01xxxxxxxxxx
sm4e. */
- return 2426;
+ return 2430;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx11xxxxxxxxxx
sm3tt2b. */
- return 2423;
+ return 2427;
}
}
}
10987654321098765432109876543210
xx101110xx0xxxxx100101xxxxxxxxxx
udot. */
- return 2407;
+ return 2411;
}
}
else
10987654321098765432109876543210
xx101110xx0xxxxx101x01xxxxxxxxxx
ummla. */
- return 2483;
+ return 2487;
}
else
{
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2499;
+ return 2503;
}
else
{
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2497;
+ return 2501;
}
else
{
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2504;
+ return 2508;
}
else
{
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2503;
+ return 2507;
}
}
}
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2500;
+ return 2504;
}
else
{
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2501;
+ return 2505;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx0xxxxxxxxxxxxxxx
bcax. */
- return 2418;
+ return 2422;
}
}
else
10987654321098765432109876543210
11001110xx1xxxxx100000xxxxxxxxxx
sha512h. */
- return 2411;
+ return 2415;
}
}
}
10987654321098765432109876543210
11001110xx1xxxxx110000xxxxxxxxxx
sm3partw1. */
- return 2424;
+ return 2428;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx100010xxxxxxxxxx
sha512su1. */
- return 2414;
+ return 2418;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110010xxxxxxxxxx
sm4ekey. */
- return 2427;
+ return 2431;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100001xxxxxxxxxx
sha512h2. */
- return 2412;
+ return 2416;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110001xxxxxxxxxx
sm3partw2. */
- return 2425;
+ return 2429;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100011xxxxxxxxxx
rax1. */
- return 2416;
+ return 2420;
}
}
else
10987654321098765432109876543210
x01011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2430;
+ return 2434;
}
else
{
10987654321098765432109876543210
x11011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2434;
+ return 2438;
}
}
}
10987654321098765432109876543210
x01011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2431;
+ return 2435;
}
else
{
10987654321098765432109876543210
x11011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2435;
+ return 2439;
}
}
}
10987654321098765432109876543210
x00011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2428;
+ return 2432;
}
else
{
10987654321098765432109876543210
x10011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2432;
+ return 2436;
}
}
else
10987654321098765432109876543210
x00011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2429;
+ return 2433;
}
else
{
10987654321098765432109876543210
x10011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2433;
+ return 2437;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2436;
+ return 2440;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2440;
+ return 2444;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2437;
+ return 2441;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2441;
+ return 2445;
}
}
else
10987654321098765432109876543210
x0101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2438;
+ return 2442;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2442;
+ return 2446;
}
}
}
10987654321098765432109876543210
x0101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2439;
+ return 2443;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2443;
+ return 2447;
}
}
}
10987654321098765432109876543210
xx001111xxxxxxxx1110x0xxxxxxxxxx
sdot. */
- return 2410;
+ return 2414;
}
else
{
10987654321098765432109876543210
xx101111xxxxxxxx1110x0xxxxxxxxxx
udot. */
- return 2409;
+ return 2413;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx1111x0xxxxxxxxxx
sudot. */
- return 2487;
+ return 2491;
}
else
{
10987654321098765432109876543210
xx00111110xxxxxx1111x0xxxxxxxxxx
usdot. */
- return 2486;
+ return 2490;
}
}
else
10987654321098765432109876543210
xx00111101xxxxxx1111x0xxxxxxxxxx
bfdot. */
- return 2498;
+ return 2502;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx1111x0xxxxxxxxxx
bfmlalb. */
- return 2506;
+ return 2510;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx1111x0xxxxxxxxxx
bfmlalt. */
- return 2505;
+ return 2509;
}
}
}
case 824: return NULL; /* fsqrt --> NULL. */
case 832: value = 833; break; /* frintz --> frintz. */
case 833: return NULL; /* frintz --> NULL. */
- case 825: value = 2502; break; /* fcvt --> bfcvt. */
- case 2502: return NULL; /* bfcvt --> NULL. */
+ case 825: value = 2506; break; /* fcvt --> bfcvt. */
+ case 2506: return NULL; /* bfcvt --> NULL. */
case 834: value = 835; break; /* frinta --> frinta. */
case 835: return NULL; /* frinta --> NULL. */
case 836: value = 837; break; /* frintx --> frintx. */
case 33:
case 34:
case 35:
- case 221:
+ case 222:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 189:
case 190:
case 215:
- case 220:
+ case 221:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 219:
return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ case 220:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
default: assert (0); abort ();
}
}
return true;
}
+bool
+aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ aarch64_insn fld_rm = extract_field (self->fields[0], code, 0);
+ aarch64_insn fld_pn = extract_field (self->fields[1], code, 0);
+ aarch64_insn fld_i1 = extract_field (self->fields[2], code, 0);
+ aarch64_insn fld_tszh = extract_field (self->fields[3], code, 0);
+ aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0);
+ int imm;
+
+ info->za_tile_vector.regno = fld_pn;
+ info->za_tile_vector.index.regno = fld_rm + 12;
+
+ if (fld_tszh == 0x1 && fld_tszl == 0x0)
+ {
+ info->qualifier = AARCH64_OPND_QLF_S_D;
+ imm = fld_i1;
+ }
+ else if (fld_tszl == 0x4)
+ {
+ info->qualifier = AARCH64_OPND_QLF_S_S;
+ imm = (fld_i1 << 1) | fld_tszh;
+ }
+ else if ((fld_tszl & 0x3) == 0x2)
+ {
+ info->qualifier = AARCH64_OPND_QLF_S_H;
+ imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
+ }
+ else if (fld_tszl & 0x1)
+ {
+ info->qualifier = AARCH64_OPND_QLF_S_B;
+ imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
+ }
+ else
+ return false;
+
+ info->za_tile_vector.index.imm = imm;
+ return true;
+}
+
/* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
array specifies which field to use for Zn. MM is encoded in the
concatenation of imm5 and SVE_tszh, with imm5 being the less
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl);
AARCH64_DECL_OPD_EXTRACTOR (ext_sme_sm_za);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sme_pred_reg_with_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_2}, "ZA array"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_2}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
{ 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */
{ 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
+ { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
+ { 23, 1 }, /* SME_i1: immediate field, bit 23. */
+ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
+ { 18, 3 }, /* SME_tshl: immediate and qualifier field, bits [20:18]. */
{ 11, 2 }, /* rotate1: FCMLA immediate rotate. */
{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
snprintf (buf, size, "%s", opnd->reg.regno == 's' ? "sm" : "za");
break;
+ case AARCH64_OPND_SME_PnT_Wm_imm:
+ snprintf (buf, size, "p%d.%s[w%d, %d]",
+ opnd->za_tile_vector.regno,
+ aarch64_get_qualifier_name (opnd->qualifier),
+ opnd->za_tile_vector.index.regno,
+ opnd->za_tile_vector.index.imm);
+ break;
+
case AARCH64_OPND_CRn:
case AARCH64_OPND_CRm:
snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
FLD_SME_Rv,
FLD_SME_Pm,
FLD_SME_zero_mask,
+ FLD_SME_Rm,
+ FLD_SME_i1,
+ FLD_SME_tszh,
+ FLD_SME_tszl,
FLD_rotate1,
FLD_rotate2,
FLD_rotate3,
{ \
QLF3(S_B,P_Z,S_B), \
}
+#define OP_SVE_NN_BHSD \
+{ \
+ QLF3(NIL,NIL,S_B), \
+ QLF3(NIL,NIL,S_H), \
+ QLF3(NIL,NIL,S_S), \
+ QLF3(NIL,NIL,S_D) \
+}
#define OP_SVE_BZBB \
{ \
QLF4(S_B,P_Z,S_B,S_B), \
{ \
QLF3(S_D,P_M,S_D), \
}
+#define OP_SVE_QMQ \
+{ \
+ QLF3(S_Q,P_M,S_Q), \
+}
#define OP_SVE_DMH \
{ \
QLF3(S_D,P_M,S_H), \
SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1),
SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1),
+ SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
+ SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
+ SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
+ SME_INSN ("psel", 0x25204000, 0xff20c000, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \
F(FLD_CRm), \
"streaming mode") \
+ Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
+ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
+ "Source scalable predicate register with index ") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
"a 16-bit unsigned immediate for TME tcancel") \
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
projects / binutils-gdb.git / commitdiff