MIPS: Create an artificial control register to hold the thread pointer.

In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.

The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.

diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 50726cd306e5186148365853b11ad3d968d862d6..27cb4357a27e2582f99f1aa3614e7b5c33be4f26 100644 (file)
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -109,8 +109,11 @@ def operands {{
     #LL Flag
     'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
 
+    #Thread pointer value for SE mode
+    'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
+
     # Index Register
-    'Index':('ControlReg','uw','MISCREG_INDEX',None,1),
+    'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
 
 
     'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),

diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index fdb04b1312644f9fc2bdb574da5b8c1e1cf9bf5a..5cf76634d2d3e7445d56e67d4bda6edea252774a 100644 (file)
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -275,6 +275,7 @@ enum MiscRegIndex{
     MISCREG_DESAVE = 248,       //Bank 31: 248-256
 
     MISCREG_LLFLAG = 257,
+    MISCREG_TP_VALUE,
 
     MISCREG_NUMREGS
 };