use alpha-numeric footnote numbering

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 21e9ce4ae246e548dbbfcfd18c2d9f86483647d2..dcc9f52d2ac42c4abda78d8f14ab6dc4f16f1148 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -4,9 +4,9 @@
 |---------------|--------------|-----------------|--------------------|-------------------|--------------------|-------------|----------------|-----------------|--------|----------------|-----------------------|----------------|-------------|--------------|
 |SVP64          |5 [^1]        |see [^2]         |Scalable [^3]       |yes                |yes                 |yes [^4]     |no [^5]         |see [^6]         |yes[^7] |yes [^8]        |yes [^9]               |yes [^10]       |yes [^11]    | yes[^12]     |
 |VSX            |700+          |700?[^v1]        |PackedSIMD          |no                 |no                  |no           |yes [^v2]       |yes              |no      |no              |no                     |no              |yes [^v3]    | no           |
-|NEON           |~250 [^n1]    |7088 [^n2]       |PackedSIMD          |no                 |no                  |no           |yes             |see [^35]        |no      |no              |no                     |no              |no           | no           |
-|SVE2           |~1000 [^e1]   |6040 [^e2]       |Predicated SIMD[^e3]|no [^e3]           |yes                 |no           |yes             |see [^35]        |no      |yes [^8]        |no                     |no              |yes [^e4]    | no           |
-|AVX512 [^x1]   |~1000s [^x2]  |7256 [^x3]       |Predicated SIMD     |no                 |yes                 |no           |yes             |see [^35]        |no      |no              |no                     |no              |yes [^x4]    | no           |
+|NEON           |~250 [^n1]    |7088 [^n2]       |PackedSIMD          |no                 |no                  |no           |yes             |see [^b1]        |no      |no              |no                     |no              |no           | no           |
+|SVE2           |~1000 [^e1]   |6040 [^e2]       |Predicated SIMD[^e3]|no [^e3]           |yes                 |no           |yes             |see [^b1]        |no      |yes [^8]        |no                     |no              |yes [^e4]    | no           |
+|AVX512 [^x1]   |~1000s [^x2]  |7256 [^x3]       |Predicated SIMD     |no                 |yes                 |no           |yes             |see [^b1]        |no      |no              |no                     |no              |yes [^x4]    | no           |
 |RVV [^r1]      |~190 [^r2]    |~25000[^r3]      |Scalable[^r4]       |yes                |yes                 |no           |yes             |yes [^r5]        |no      |yes             |no                     |no              |no           | no           |
 |Aurora SX[^s1] |~200 [^s2]    |unknown [^s3]    |Scalable [^s4]      |yes                |yes                 |no           |yes             |no               |no      |no              |no                     |no              |?            | no           |
 |66000[^m1]     |~200          |unknown          |AutoVec[^m1]        |see [^m1]          |see[^m1]            |no           |see [^m1]       |no               |yes[^m2]|see [^m1]       |no                     |no              |no           | no           |
@@ -54,6 +54,6 @@
     [SMOPA](https://developer.arm.com/documentation/ddi0602/2022-06/SME-Instructions/SMOPA--Signed-integer-sum-of-outer-products-and-accumulate-?lang=en)
     which are power-2 based on Silicon-partner SIMD width. Non-power-2 not supported but [zero-input masking](https://www.realworldtech.com/forum/?threadid=202688&curpostid=207774) is.
 [^x4]: [Advanced matrix Extensions](https://en.wikipedia.org/wiki/Advanced_Matrix_Extensions) supports BF16 and INT8 only. Separate regfile, power-of-two "tiles". Not general-purpose at all.
-[^35]: Although registers may be 128-bit in NEON, SVE2, and AVX, unlike VSX there are very few (or no) actual arithmetic 128-bit operations. Only RVV and SVP64 have the possibility of 128-bit ops 
+[^b1]: Although registers may be 128-bit in NEON, SVE2, and AVX, unlike VSX there are very few (or no) actual arithmetic 128-bit operations. Only RVV and SVP64 have the possibility of 128-bit ops 
 [^m1]: Mitch Alsup's MyISA 66000 is available on request. A powerful RISC ISA with a **Hardware-level auto-vectorisation** LOOP built-in as an extension named VVM.  Classified as "Vertical-First".
 [^m2]: MyISA 66000 has a CARRY register up to 64-bit. Repeated application of FMA (esp. within Auto-Vectored LOOPS) automatically and inherently creates big-int operations with zero effort.