vendor.xilinx_{7series,ultrascale}: add SIM_DEVICE parameter.

The parameter defaults to "ULTRASCALE", even when synthesizing for
7-series devices. This could lead to a simulation/synthesis mismatch,
and causes a warning.

Fixes #438.

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 6e3017ff3555598f5934ae06317824d2695e94fb..8b99ca52869f96e447d99d422325a774271e6294 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -168,7 +168,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
             ready = Signal()
             m.submodules += Instance("STARTUPE2", o_EOS=ready)
             m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
-            m.submodules += Instance("BUFGCE", i_CE=ready, i_I=clk_i, o_O=ClockSignal("sync"))
+            m.submodules += Instance("BUFGCE",
+                p_SIM_DEVICE="7SERIES",
+                i_CE=ready,
+                i_I=clk_i,
+                o_O=ClockSignal("sync")
+            )
             if self.default_rst is not None:
                 m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
             return m

diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 19bbeae286aac12c43f16930263e04b137192a62..a22b335cbf1f4441106fcf4a2006a8778ffa9ff9 100644 (file)
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -168,7 +168,12 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
             ready = Signal()
             m.submodules += Instance("STARTUPE3", o_EOS=ready)
             m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
-            m.submodules += Instance("BUFGCE", i_CE=ready, i_I=clk_i, o_O=ClockSignal("sync"))
+            m.submodules += Instance("BUFGCE",
+                p_SIM_DEVICE="ULTRASCALE",
+                i_CE=ready,
+                i_I=clk_i,
+                o_O=ClockSignal("sync")
+            )
             if self.default_rst is not None:
                 m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
             return m