radv: Emit enqueued pipeline barriers on event write.

Since the CPU can read them we need to execute any GPU->CPU
flushes before the event is written.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 339704990e26137d9902d0874b1d6917e19d0473..e21aaa9535d824f9a7b2b5f620ee6d90ade6646f 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4337,6 +4337,8 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
        struct radeon_cmdbuf *cs = cmd_buffer->cs;
        uint64_t va = radv_buffer_get_va(event->bo);
 
+       si_emit_cache_flush(cmd_buffer);
+
        radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
 
        MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);