Use read_args for read_verilog

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 16b607aacae5089da30249aefe4c0d0b13a4ef9b..caeeb3266afb4b8f24b64c7a05f25b5ea5eeec0d 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,10 +283,13 @@ struct SynthXilinxPass : public ScriptPass
                        ff_map_file = "+/xilinx/xc7_ff_map.v";
 
                if (check_label("begin")) {
+                       std::string read_args;
                        if (vpr)
-                               run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
-                       else
-                               run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
+                               read_args += " -D_EXPLICIT_CARRY";
+                       if (abc9)
+                               read_args += " -D_ABC9";
+                       read_args += " -lib +/xilinx/cells_sim.v";
+                       run("read_verilog" + read_args);
 
                        if (help_mode)
                                run("read_verilog -lib +/xilinx/{family}_cells_xtra.v");