CR0 (if Rc=1)
+# GPR Dynamic Binary Logic
+
+BM2-Form
+
+* binlog RT,RA,RB,RC,nh
+
+Pseudo-code:
+
+ if nh = 1 then lut <- (RC)[56:59]
+ else lut <- (RC)[60:63]
+ result <- [0] * 64
+ do i = 0 to 63
+ idx <- (RA)[i] || (RB)[i]
+ result[i] <- lut[3-idx]
+ RT <- result
+
+Description:
+
+ If nh contains a 0, let lut be the four LSBs of RC
+ (bits 60 to 63). Otherwise let lut be the next
+ four LSBs of RC (bits 56 to 59).
+
+ Let j be the value of the concatenation of the
+ contents of bit i of RT with bit i of RB.
+
+ The value of bit j of lut is placed into bit i of RT.
+
+Special registers altered:
+
+ None
+
# Condition Register Ternary Bitwise Logic Immediate
CRB-Form
CR field BF
+# Condition Register Field Dynamic Binary Logic
+
+CRB-Form
+
+* crbinlog BF,BFA,BFB,msk
+
+Pseudo-code:
+
+ a <- CR[4*BF+32:4*BFA+35]
+ b <- CR[4*BFA+32:4*BFA+35]
+ lut <- CR[4*BFB+32:4*BFB+35]
+
+ result <- [0] * 4
+ do i = 0 to 3
+ idx <- a[i] || b[i]
+ result[i] <- lut[3-idx]
+ do i = 0 to 3
+ if msk[i] = 1 then
+ CR[4*BF+32+i] <- result[i]
+
+Description:
+
+ For each integer value i, 0 to 3, do the following.
+
+ Let j be the value of the concatenation of the
+ contents of bit i of CR Field BF with bit i of CR Field BFA.
+
+ If bit i of msk is set to 1 then the value of bit j of
+ CR Field BFB is placed into bit i of CR Field BF.
+
+ Otherwise, if bit i of msk is a zero then bit i of
+ CR Field BF is unchanged.
+
+ If `msk` is zero an Illegal Instruction trap is raised.
+
+Special registers altered:
+
+ CR field BF
+
# Add With Shift By Immediate
Z23-Form
# 1.6.2.2 BM2-FORM
|0 |6 |11 |16 |21 |26 |27 31|
| PO | RT | RA | RB |bm |L | XO |
+ | PO | RT | RA | RB |RC |nh | XO |
# 1.6.2.2 CRB-FORM
|0 |6 |9 |11 |14 | 16 |19 |26 | 31|
Field used to specify the number of bytes to move
in an immediate Move Assist instruction.
Formats: X
+ nh (26)
+ Field used to specify which half of RC to select as a
+ LUT2 (4-bit lookup) table.
+ Formats: BM2
OC (6:20)
Field used by the Embedded Hypervisor Privilege
instruction.
RC (21:25)
Field used to specify a GPR to be used as a
source.
- Formats: VA, VA2, SVD, SVDS
+ Formats: VA, VA2, SVD, SVDS, BM2
Rc (31)
RECORD bit.
0 Do not alter the Condition Register.
------01001,ALU,OP_MADDRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
------01011,ALU,OP_MSUBRS,RA,CONST_SH,RB,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,msubrs,A,,1,unofficial until submitted and approved/renumbered by the opf isa wg
0101110110-,ALU,OP_BMAT,RA,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,gbbd,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------00001,SHIFT_ROT,OP_BINLOG,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,binlog,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+-----001001,CR,OP_CRBINLOG,NONE,NONE,NONE,NONE,BFA_BFB_BF,BF,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,crbinlog,CRB,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+
"brh", "brw", "brd",
'setvl', 'svindex', 'svremap', 'svstep',
'svshape', 'svshape2',
- 'crternlogi', 'ternlogi', 'bmask', 'cprop', 'gbbd',
+ 'binlog', 'crbinlog', 'crternlogi', 'ternlogi',
+ 'bmask', 'cprop', 'gbbd',
'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
"dsld", "dsrd", "maddedus",
"cprop", # AV bitmanip
"crand", "crandc", "creqv",
"crnand", "crnor", "cror", "crorc", "crxor",
+ "crbinlog", # binary bitmanip
"crternlogi", # ternary bitmanip
"darn",
"dcbf", "dcbst", "dcbt", "dcbtst", "dcbz",
"subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
"subfme", "subfmeo", "subfo", "subfze", "subfzeo",
"sync",
- "ternlogi",
+ "binlog", "ternlogi", # binary/ternary (lut2/lut3)
"td", "tdi",
"tlbie", "tlbiel", "tlbsync",
"tw", "twi",
OP_SETBC = 111
OP_BMAT = 112 # bmatflip/xor/and - known by many names (vgbbd in Power)
OP_CRTERNLOG = 113
+ OP_BINLOG = 114
+ OP_CRBINLOG = 115
class SelType(Enum):
class CRIn2Sel(Enum):
NONE = 0
BB = 1
+ BFB = 2
def __str__(self):
return self.name
e.crregs[0] = (eq << 1) | (gt << 2) | (lt << 3)
self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+ def do_case_binlog(self, ra, rb, rc, nh):
+ lst = ["binlog 3, 4, 5, 6, %d" % nh]
+ initial_regs = [0] * 32
+ initial_regs[4] = ra
+ initial_regs[5] = rb
+ initial_regs[6] = rc
+ lut = rc & 0b11111111 # one of two 4-bit LUTs is in 1st 8 bits
+ if nh == 1: # top half (bits 4-7... sigh MSB 56-59) else 0-3 (60-63)
+ lut = lut >> 4
+ lut = lut & 0b1111
+ lst = list(SVP64Asm(lst, bigendian))
+ e = ExpectedState(pc=4)
+ expected = 0
+ for i in range(64):
+ lut_index = 0
+ if rb & 2 ** i:
+ lut_index |= 2 ** 0
+ if ra & 2 ** i:
+ lut_index |= 2 ** 1
+ if lut & 2 ** lut_index:
+ expected |= 2 ** i
+ e.intregs[3] = expected
+ e.intregs[4] = ra
+ e.intregs[5] = rb
+ e.intregs[6] = rc
+ self.add_case(Program(lst, bigendian), initial_regs, expected=e)
+
+ def case_binlog_0(self):
+ self.do_case_binlog(0x8000_0000_FFFF_0000,
+ 0x8000_0000_FF00_FF00,
+ 0x80, 1)
+ self.do_case_binlog(0x8000_0000_FFFF_0000,
+ 0x8000_0000_FF00_FF00,
+ 0x80, 0)
+
+ def case_binlog_random(self):
+ for i in range(100):
+ ra = hash_256(f"binlog ra {i}") % 2 ** 64
+ rb = hash_256(f"binlog rb {i}") % 2 ** 64
+ rc = hash_256(f"binlog rc {i}") % 2 ** 8
+ nh = hash_256(f"binlog nh {i}") & 0b1
+ self.do_case_binlog(ra, rb, rc, nh)
+
def do_case_grev(self, w, is_imm, ra, rb):
bits = 32 if w else 64
masked_rb = rb % bits
projects / openpower-isa.git / commitdiff