OpClass __opClass) :
X86ISA::X86StaticInst(_mnemonic, _machInst, __opClass)
{
+ flags[IsSerializing] = 1;
+ flags[IsSerializeAfter] = 1;
}
std::string generateDisassembly(Addr pc,
def macroop WRMSR
{
+ .serializing
mov t2, t2, rax, dataSize=4
slli t3, rdx, 32, dataSize=8
or t2, t2, t3, dataSize=8
microcode = '''
def macroop LGDT_M
{
+ .serializing
.adjust_env maxOsz
# Get the limit
def macroop LGDT_P
{
+ .serializing
.adjust_env maxOsz
rdip t7
def macroop LGDT_16_M
{
+ .serializing
.adjust_env maxOsz
# Get the limit
def macroop LGDT_16_P
{
+ .serializing
.adjust_env maxOsz
rdip t7
def macroop LIDT_M
{
+ .serializing
.adjust_env maxOsz
# Get the limit
def macroop LIDT_P
{
+ .serializing
.adjust_env maxOsz
rdip t7
def macroop LIDT_16_M
{
+ .serializing
.adjust_env maxOsz
# Get the limit
def macroop LIDT_16_P
{
+ .serializing
.adjust_env maxOsz
rdip t7
def macroop LTR_R
{
+ .serializing
chks reg, t0, TRCheck
limm t4, 0, dataSize=8
srli t4, reg, 3, dataSize=2
def macroop LTR_M
{
+ .serializing
ld t5, seg, sib, disp, dataSize=2
chks t5, t0, TRCheck
limm t4, 0, dataSize=8
def macroop LTR_P
{
+ .serializing
rdip t7
ld t5, seg, riprel, disp, dataSize=2
chks t5, t0, TRCheck
def macroop LLDT_R
{
+ .serializing
chks reg, t0, InGDTCheck, flags=(EZF,)
br label("end"), flags=(CEZF,)
limm t4, 0, dataSize=8
def macroop LLDT_M
{
+ .serializing
ld t5, seg, sib, disp, dataSize=2
chks t5, t0, InGDTCheck, flags=(EZF,)
br label("end"), flags=(CEZF,)
def macroop LLDT_P
{
+ .serializing
rdip t7
ld t5, seg, riprel, disp, dataSize=2
chks t5, t0, InGDTCheck, flags=(EZF,)