pysvp64asm: support /sea specifier

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 71b8697536525134a10196936f3eaabf583f95f8..b3bae0d0283b2af2680ce74b0fa2321b6d333db1 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1064,6 +1064,7 @@ class SVP64Asm:
         ldst_elstride = 0
 
         vli = False
+        sea = False
 
         # ok let's start identifying opcode augmentation fields
         for encmode in opmodes:
@@ -1363,6 +1364,9 @@ class SVP64Asm:
         if sv_mode&2:
             mode |= (0b1<<SVP64MODE.MOD2_MSB)
 
+        if sea:
+            mode |= (0b1 << SVP64MODE.SEA)
+
         if not is_bc:
             svp64_rm.mode = mode      # mode: bits 19-23
             if vli: