+2019-08-07 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/iterators.md (UNSPEC_COND_FABS, UNSPEC_COND_FNEG)
+ (UNSPEC_COND_FRINTA, UNSPEC_COND_FRINTI, UNSPEC_COND_FRINTM)
+ (UNSPEC_COND_FRINTN, UNSPEC_COND_FRINTP, UNSPEC_COND_FRINTX)
+ (UNSPEC_COND_FRINTZ, UNSPEC_COND_FSQRT): New unspecs.
+ (optab, sve_fp_op): Handle them.
+ (SVE_FP_UNARY): Delete.
+ (optab): Remove sqrt entry.
+ (sve_fp_op): Remove neg, abs and sqrt entries.
+ (SVE_COND_FP_UNARY): New int iterator.
+ * config/aarch64/aarch64-sve.md (<frint_pattern><mode>2)
+ (*<frint_pattern><mode>2): Delete.
+ (<SVE_FP_UNARY:optab><SVE_F:mode>2): Replace with...
+ (<SVE_COND_FP_UNARY:optab><SVE_F:mode>2): ...this.
+ (*<SVE_FP_UNARY:optab><SVE_F:mode>2): Replace with...
+ (*<SVE_COND_FP_UNARY:optab><SVE_F:mode>2): ...this.
+
2019-08-07 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete.
;;
;; == Unary arithmetic
;; ---- [INT] General unary arithmetic corresponding to rtx codes
-;; ---- [FP] General unary arithmetic corresponding to rtx codes
-;; ---- [FP] Rounding
+;; ---- [FP] General unary arithmetic corresponding to unspecs
;; ---- [PRED] Inverse
;; == Binary arithmetic
)
;; -------------------------------------------------------------------------
-;; ---- [FP] General unary arithmetic corresponding to rtx codes
+;; ---- [FP] General unary arithmetic corresponding to unspecs
;; -------------------------------------------------------------------------
;; Includes:
;; - FABS
;; - FNEG
-;; - FSQRT
-;; -------------------------------------------------------------------------
-
-;; Unpredicated floating-point unary operations.
-(define_expand "<optab><mode>2"
- [(set (match_operand:SVE_F 0 "register_operand")
- (unspec:SVE_F
- [(match_dup 2)
- (SVE_FP_UNARY:SVE_F (match_operand:SVE_F 1 "register_operand"))]
- UNSPEC_MERGE_PTRUE))]
- "TARGET_SVE"
- {
- operands[2] = aarch64_ptrue_reg (<VPRED>mode);
- }
-)
-
-;; Predicated floating-point unary operations.
-(define_insn "*<optab><mode>2"
- [(set (match_operand:SVE_F 0 "register_operand" "=w")
- (unspec:SVE_F
- [(match_operand:<VPRED> 1 "register_operand" "Upl")
- (SVE_FP_UNARY:SVE_F (match_operand:SVE_F 2 "register_operand" "w"))]
- UNSPEC_MERGE_PTRUE))]
- "TARGET_SVE"
- "<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
-)
-
-;; -------------------------------------------------------------------------
-;; ---- [FP] Rounding
-;; -------------------------------------------------------------------------
-;; Includes:
;; - FRINTA
;; - FRINTI
;; - FRINTM
;; - FRINTP
;; - FRINTX
;; - FRINTZ
+;; - FSQRT
;; -------------------------------------------------------------------------
-;; Unpredicated FRINTy.
-(define_expand "<frint_pattern><mode>2"
+;; Unpredicated floating-point unary operations.
+(define_expand "<optab><mode>2"
[(set (match_operand:SVE_F 0 "register_operand")
(unspec:SVE_F
[(match_dup 2)
- (unspec:SVE_F [(match_operand:SVE_F 1 "register_operand")]
- FRINT)]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SVE_F 1 "register_operand")]
+ SVE_COND_FP_UNARY))]
"TARGET_SVE"
{
operands[2] = aarch64_ptrue_reg (<VPRED>mode);
}
)
-;; FRINTy predicated with a PTRUE.
-(define_insn "*<frint_pattern><mode>2"
+;; Predicated floating-point unary operations.
+(define_insn "*<optab><mode>2"
[(set (match_operand:SVE_F 0 "register_operand" "=w")
(unspec:SVE_F
[(match_operand:<VPRED> 1 "register_operand" "Upl")
- (unspec:SVE_F [(match_operand:SVE_F 2 "register_operand" "w")]
- FRINT)]
- UNSPEC_MERGE_PTRUE))]
+ (match_operand:SVE_F 2 "register_operand" "w")]
+ SVE_COND_FP_UNARY))]
"TARGET_SVE"
- "frint<frint_suffix>\t%0.<Vetype>, %1/m, %2.<Vetype>"
+ "<sve_fp_op>\t%0.<Vetype>, %1/m, %2.<Vetype>"
)
;; -------------------------------------------------------------------------
[(set (match_operand:SVE_F 0 "register_operand" "=w")
(unspec:SVE_F
[(match_operand:<VPRED> 1 "register_operand" "Upl")
- (abs:SVE_F
- (minus:SVE_F
- (match_operand:SVE_F 2 "register_operand" "0")
- (match_operand:SVE_F 3 "register_operand" "w")))]
- UNSPEC_MERGE_PTRUE))]
+ (minus:SVE_F
+ (match_operand:SVE_F 2 "register_operand" "0")
+ (match_operand:SVE_F 3 "register_operand" "w"))]
+ UNSPEC_COND_FABS))]
"TARGET_SVE"
"fabd\t%0.<Vetype>, %1/m, %2.<Vetype>, %3.<Vetype>"
)
UNSPEC_XORF ; Used in aarch64-sve.md.
UNSPEC_SMUL_HIGHPART ; Used in aarch64-sve.md.
UNSPEC_UMUL_HIGHPART ; Used in aarch64-sve.md.
+ UNSPEC_COND_FABS ; Used in aarch64-sve.md.
UNSPEC_COND_FADD ; Used in aarch64-sve.md.
UNSPEC_COND_FCMEQ ; Used in aarch64-sve.md.
UNSPEC_COND_FCMGE ; Used in aarch64-sve.md.
UNSPEC_COND_FMLA ; Used in aarch64-sve.md.
UNSPEC_COND_FMLS ; Used in aarch64-sve.md.
UNSPEC_COND_FMUL ; Used in aarch64-sve.md.
+ UNSPEC_COND_FNEG ; Used in aarch64-sve.md.
UNSPEC_COND_FNMLA ; Used in aarch64-sve.md.
UNSPEC_COND_FNMLS ; Used in aarch64-sve.md.
+ UNSPEC_COND_FRINTA ; Used in aarch64-sve.md.
+ UNSPEC_COND_FRINTI ; Used in aarch64-sve.md.
+ UNSPEC_COND_FRINTM ; Used in aarch64-sve.md.
+ UNSPEC_COND_FRINTN ; Used in aarch64-sve.md.
+ UNSPEC_COND_FRINTP ; Used in aarch64-sve.md.
+ UNSPEC_COND_FRINTX ; Used in aarch64-sve.md.
+ UNSPEC_COND_FRINTZ ; Used in aarch64-sve.md.
+ UNSPEC_COND_FSQRT ; Used in aarch64-sve.md.
UNSPEC_COND_FSUB ; Used in aarch64-sve.md.
UNSPEC_LASTB ; Used in aarch64-sve.md.
UNSPEC_FCADD90 ; Used in aarch64-simd.md.
;; SVE integer unary operations.
(define_code_iterator SVE_INT_UNARY [abs neg not popcount])
-;; SVE floating-point unary operations.
-(define_code_iterator SVE_FP_UNARY [abs neg sqrt])
-
;; SVE integer binary operations.
(define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin
and ior xor])
(leu "leu")
(geu "geu")
(gtu "gtu")
- (abs "abs")
- (sqrt "sqrt")])
+ (abs "abs")])
;; For comparison operators we use the FCM* and CM* instructions.
;; As there are no CMLE or CMLT instructions which act on 3 vector
;; The floating-point SVE instruction that implements an rtx code.
(define_code_attr sve_fp_op [(plus "fadd")
(minus "fsub")
- (mult "fmul")
- (neg "fneg")
- (abs "fabs")
- (sqrt "fsqrt")])
+ (mult "fmul")])
;; The SVE immediate constraint to use for an rtl code.
(define_code_attr sve_imm_con [(eq "vsc")
(define_int_iterator MUL_HIGHPART [UNSPEC_SMUL_HIGHPART UNSPEC_UMUL_HIGHPART])
+(define_int_iterator SVE_COND_FP_UNARY [UNSPEC_COND_FABS
+ UNSPEC_COND_FNEG
+ UNSPEC_COND_FRINTA
+ UNSPEC_COND_FRINTI
+ UNSPEC_COND_FRINTM
+ UNSPEC_COND_FRINTN
+ UNSPEC_COND_FRINTP
+ UNSPEC_COND_FRINTX
+ UNSPEC_COND_FRINTZ
+ UNSPEC_COND_FSQRT])
+
(define_int_iterator SVE_COND_FP_BINARY [UNSPEC_COND_FADD
UNSPEC_COND_FDIV
UNSPEC_COND_FMAXNM
(UNSPEC_ANDV "and")
(UNSPEC_IORV "ior")
(UNSPEC_XORV "xor")
+ (UNSPEC_COND_FABS "abs")
(UNSPEC_COND_FADD "add")
(UNSPEC_COND_FDIV "div")
(UNSPEC_COND_FMAXNM "smax")
(UNSPEC_COND_FMLA "fma")
(UNSPEC_COND_FMLS "fnma")
(UNSPEC_COND_FMUL "mul")
+ (UNSPEC_COND_FNEG "neg")
(UNSPEC_COND_FNMLA "fnms")
(UNSPEC_COND_FNMLS "fms")
+ (UNSPEC_COND_FRINTA "round")
+ (UNSPEC_COND_FRINTI "nearbyint")
+ (UNSPEC_COND_FRINTM "floor")
+ (UNSPEC_COND_FRINTN "frintn")
+ (UNSPEC_COND_FRINTP "ceil")
+ (UNSPEC_COND_FRINTX "rint")
+ (UNSPEC_COND_FRINTZ "btrunc")
+ (UNSPEC_COND_FSQRT "sqrt")
(UNSPEC_COND_FSUB "sub")])
(define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
(UNSPEC_COND_FCMLT "lt")
(UNSPEC_COND_FCMNE "ne")])
-(define_int_attr sve_fp_op [(UNSPEC_COND_FADD "fadd")
+(define_int_attr sve_fp_op [(UNSPEC_COND_FABS "fabs")
+ (UNSPEC_COND_FADD "fadd")
(UNSPEC_COND_FDIV "fdiv")
(UNSPEC_COND_FMAXNM "fmaxnm")
(UNSPEC_COND_FMINNM "fminnm")
(UNSPEC_COND_FMUL "fmul")
+ (UNSPEC_COND_FNEG "fneg")
+ (UNSPEC_COND_FRINTA "frinta")
+ (UNSPEC_COND_FRINTI "frinti")
+ (UNSPEC_COND_FRINTM "frintm")
+ (UNSPEC_COND_FRINTN "frintn")
+ (UNSPEC_COND_FRINTP "frintp")
+ (UNSPEC_COND_FRINTX "frintx")
+ (UNSPEC_COND_FRINTZ "frintz")
+ (UNSPEC_COND_FSQRT "fsqrt")
(UNSPEC_COND_FSUB "fsub")])
(define_int_attr sve_fp_op_rev [(UNSPEC_COND_FADD "fadd")
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