Added design->select() api and use it in extract pass

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index b5338a33c26027db5c2af12f3fee6ec5e90f418f..a0d7a1a37cd9b91a80437666cbbbcb08a5cab1ee 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -212,6 +212,13 @@ struct RTLIL::Design {
        template<typename T1, typename T2> bool selected(T1 *module, T2 *member) {
                return selected_member(module->name, member->name);
        }
+       template<typename T1, typename T2> void select(T1 *module, T2 *member) {
+               if (selection_stack.size() > 0) {
+                       RTLIL::Selection &sel = selection_stack.back();
+                       if (!sel.full_selection && sel.selected_modules.count(module->name) == 0)
+                               sel.selected_members[module->name].insert(member->name);
+               }
+       }
 };
 
 struct RTLIL::Module {

diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc
index 3e5e4afb2811cff200b29c5614a965e97f144ae0..e6bb1ca3025206a867943f10ca6cbc5e198ce8ce 100644 (file)
--- a/passes/extract/extract.cc
+++ b/passes/extract/extract.cc
@@ -156,7 +156,7 @@ namespace
                return true;
        }
 
-       void replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
+       RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
        {
                SigMap sigmap(needle);
                SigSet<std::pair<std::string, int>> sig2port;
@@ -202,6 +202,8 @@ namespace
                        haystack->cells.erase(haystack_cell->name);
                        delete haystack_cell;
                }
+
+               return cell;
        }
 }
 
@@ -451,7 +453,9 @@ struct ExtractPass : public Pass {
                                                        log(" %s:%s", it2.first.c_str(), it2.second.c_str());
                                                log("\n");
                                        }
-                                       replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
+                                       RTLIL::Cell *new_cell = replace(needle_map.at(result.needleGraphId), haystack_map.at(result.haystackGraphId), result);
+                                       design->select(haystack_map.at(result.haystackGraphId), new_cell);
+                                       log("  new cell: %s\n", id2cstr(new_cell->name));
                                }
                        }
                }