ecp5 to use -max_iter 1
authorEddie Hung <eddie@fpgeh.com>
Wed, 21 Aug 2019 02:18:36 +0000 (19:18 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 21 Aug 2019 02:18:36 +0000 (19:18 -0700)
techlibs/ecp5/abc_map.v
techlibs/ecp5/cells_sim.v
techlibs/ecp5/synth_ecp5.cc

index e8187ed18209c25b8b28a514894894866cbdd75d..ffd25f06d949e7d9caacab1491397d21eade0b72 100644 (file)
@@ -13,7 +13,7 @@ module TRELLIS_DPR16X4 (
        parameter [63:0] INITVAL = 64'h0000000000000000;
     wire [3:0] \$DO ;
 
-    \$__ABC_DPR16X4_SEQ #(
+    TRELLIS_DPR16X4 #(
       .WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
     ) _TECHMAP_REPLACE_ (
       .DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
index f79a2731270c76dcc32af4649595b6fe655b4615..24de0c3c2bd44ad47b76faa2f7191f504ed68ced 100644 (file)
@@ -113,7 +113,7 @@ module TRELLIS_DPR16X4 (
        input        WRE,
        input        WCK,
        input  [3:0] RAD,
-       output [3:0] DO
+       /* (* abc_arrival=<TODO> *) */ output [3:0] DO
 );
        parameter WCKMUX = "WCK";
        parameter WREMUX = "WRE";
index 93e1cd5b5a28204604f21eb76b18de70f85ce401..b1d3160bae95ed1d48613f5037642b2134e0b8e1 100644 (file)
@@ -280,11 +280,10 @@ struct SynthEcp5Pass : public ScriptPass
                        }
                        std::string techmap_args = "-map +/ecp5/latches_map.v";
                        if (abc9)
-                               techmap_args += " -map +/ecp5/abc_map.v";
+                               techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
                        run("techmap " + techmap_args);
 
                        if (abc9) {
-                               run("read_verilog -icells -lib +/ecp5/abc_model.v");
                                if (nowidelut)
                                        run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
                                else