parameter [63:0] INITVAL = 64'h0000000000000000;
wire [3:0] \$DO ;
- \$__ABC_DPR16X4_SEQ #(
+ TRELLIS_DPR16X4 #(
.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
) _TECHMAP_REPLACE_ (
.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
input WRE,
input WCK,
input [3:0] RAD,
- output [3:0] DO
+ /* (* abc_arrival=<TODO> *) */ output [3:0] DO
);
parameter WCKMUX = "WCK";
parameter WREMUX = "WRE";
}
std::string techmap_args = "-map +/ecp5/latches_map.v";
if (abc9)
- techmap_args += " -map +/ecp5/abc_map.v";
+ techmap_args += " -map +/ecp5/abc_map.v -max_iter 1";
run("techmap " + techmap_args);
if (abc9) {
- run("read_verilog -icells -lib +/ecp5/abc_model.v");
if (nowidelut)
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
else