radeonsi: remove redundant si_texture::cmask_size

cmask_buffer and surface.cmask_size can replace its role.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 0ab1356aecdde03578e078287907701b29506cc7..72adc21b3dc141366576f29c1556beae7abad8c4 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -538,7 +538,7 @@ si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
                            unsigned first_level, unsigned last_level)
 {
        /* CMASK or DCC can be discarded and we can still end up here. */
-       if (!tex->cmask_size && !tex->surface.fmask_size && !tex->dcc_offset)
+       if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->dcc_offset)
                return;
 
        si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
@@ -859,7 +859,7 @@ static void si_decompress_subresource(struct pipe_context *ctx,
                si_decompress_depth(sctx, stex, planes,
                                    level, level,
                                    first_layer, last_layer);
-       } else if (stex->surface.fmask_size || stex->cmask_size || stex->dcc_offset) {
+       } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->dcc_offset) {
                /* If we've rendered into the framebuffer and it's a blitting
                 * source, make sure the decompression pass is invoked
                 * by dirtying the framebuffer.
@@ -1139,7 +1139,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
            info->src.box.height == dst_height &&
            info->src.box.depth == 1 &&
            !dst->surface.is_linear &&
-           (!dst->cmask_size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
+           (!dst->cmask_buffer || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
                /* Check the last constraint. */
                if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
                        /* The next fast clear will switch to this mode to
@@ -1325,7 +1325,7 @@ static void si_flush_resource(struct pipe_context *ctx,
        if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
                return;
 
-       if (!tex->is_depth && (tex->cmask_size || tex->dcc_offset)) {
+       if (!tex->is_depth && (tex->cmask_buffer || tex->dcc_offset)) {
                si_blit_decompress_color(sctx, tex, 0, res->last_level,
                                         0, util_max_layer(res, 0),
                                         tex->dcc_separate_buffer != NULL);

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 83bb51a043aeeba441242de47a5edba2f9279f41..5cbbc89b60e1f7022ffa7ed24c3bea8635ea7f3d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -37,14 +37,9 @@ enum {
 static void si_alloc_separate_cmask(struct si_screen *sscreen,
                                    struct si_texture *tex)
 {
-       if (tex->cmask_buffer)
+       if (tex->cmask_buffer || !tex->surface.cmask_size)
                 return;
 
-       assert(tex->cmask_size == 0);
-
-       if (!tex->surface.cmask_size)
-               return;
-
        tex->cmask_buffer =
                si_aligned_buffer_create(&sscreen->b,
                                         SI_RESOURCE_FLAG_UNMAPPABLE,
@@ -54,7 +49,6 @@ static void si_alloc_separate_cmask(struct si_screen *sscreen,
        if (tex->cmask_buffer == NULL)
                return;
 
-       tex->cmask_size = tex->surface.cmask_size;
        tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
        tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
 
@@ -490,13 +484,13 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                                continue;
 
                        /* DCC fast clear with MSAA should clear CMASK to 0xC. */
-                       if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_size) {
+                       if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
                                /* TODO: This doesn't work with MSAA. */
                                if (eliminate_needed)
                                        continue;
 
                                si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
-                                               tex->cmask_offset, tex->cmask_size,
+                                               tex->cmask_offset, tex->surface.cmask_size,
                                                0xCCCCCCCC, SI_COHERENCY_CB_META);
                                need_decompress_pass = true;
                        }
@@ -522,13 +516,12 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 
                        /* ensure CMASK is enabled */
                        si_alloc_separate_cmask(sctx->screen, tex);
-                       if (tex->cmask_size == 0) {
+                       if (!tex->cmask_buffer)
                                continue;
-                       }
 
                        /* Do the fast clear. */
                        si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
-                                       tex->cmask_offset, tex->cmask_size, 0,
+                                       tex->cmask_offset, tex->surface.cmask_size, 0,
                                        SI_COHERENCY_CB_META);
                        need_decompress_pass = true;
                }

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 68b58fde06faa7d4243d51ba0aa35f8725427f95..e8c028061d1af923c82ed084a51199693cc36c0e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -478,7 +478,7 @@ static bool color_needs_decompression(struct si_texture *tex)
 {
        return tex->surface.fmask_size ||
               (tex->dirty_level_mask &&
-               (tex->cmask_size || tex->dcc_offset));
+               (tex->cmask_buffer || tex->dcc_offset));
 }
 
 static bool depth_needs_decompression(struct si_texture *tex)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 7ec547d91a3b06b80762c37b5d533b3521e48613..4f18883c6a8e4e0e5d2d40be5e6688d49c72bdea 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -241,7 +241,6 @@ struct si_texture {
        uint64_t                        fmask_offset;
        uint64_t                        cmask_offset;
        uint64_t                        cmask_base_address_reg;
-       uint32_t                        cmask_size;
        struct r600_resource            *cmask_buffer;
        uint64_t                        dcc_offset; /* 0 = disabled */
        unsigned                        cb_color_info; /* fast clear enable bit */

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index f7a56c127d5d1199a7ffb8edc82258577358a23d..a577778a9f14e1b2ade7c00c77612318b1f56a75 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -82,7 +82,7 @@ bool si_prepare_for_dma_blit(struct si_context *sctx,
         *   dst: If overwriting the whole texture, discard CMASK and use
         *        SDMA. Otherwise, use the 3D path.
         */
-       if (dst->cmask_size && dst->dirty_level_mask & (1 << dst_level)) {
+       if (dst->cmask_buffer && dst->dirty_level_mask & (1 << dst_level)) {
                /* The CMASK clear is only enabled for the first level. */
                assert(dst_level == 0);
                if (!util_texrange_covers_whole_level(&dst->buffer.b.b, dst_level,
@@ -94,7 +94,7 @@ bool si_prepare_for_dma_blit(struct si_context *sctx,
        }
 
        /* All requirements are met. Prepare textures for SDMA. */
-       if (src->cmask_size && src->dirty_level_mask & (1 << src_level))
+       if (src->cmask_buffer && src->dirty_level_mask & (1 << src_level))
                sctx->b.flush_resource(&sctx->b, &src->buffer.b.b);
 
        assert(!(src->dirty_level_mask & (1 << src_level)));
@@ -420,13 +420,12 @@ void si_eliminate_fast_color_clear(struct si_context *sctx,
 void si_texture_discard_cmask(struct si_screen *sscreen,
                              struct si_texture *tex)
 {
-       if (!tex->cmask_size)
+       if (!tex->cmask_buffer)
                return;
 
        assert(tex->buffer.b.b.nr_samples <= 1);
 
        /* Disable CMASK. */
-       tex->cmask_size = 0;
        tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8;
        tex->dirty_level_mask = 0;
 
@@ -435,6 +434,8 @@ void si_texture_discard_cmask(struct si_screen *sscreen,
        if (tex->cmask_buffer != &tex->buffer)
            r600_resource_reference(&tex->cmask_buffer, NULL);
 
+       tex->cmask_buffer = NULL;
+
        /* Notify all contexts about the change. */
        p_atomic_inc(&sscreen->dirty_tex_counter);
        p_atomic_inc(&sscreen->compressed_colortex_counter);
@@ -572,7 +573,6 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
 
        tex->fmask_offset = new_tex->fmask_offset;
        tex->cmask_offset = new_tex->cmask_offset;
-       tex->cmask_size = new_tex->cmask_size;
        tex->cmask_base_address_reg = new_tex->cmask_base_address_reg;
        r600_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer);
        tex->dcc_offset = new_tex->dcc_offset;
@@ -604,7 +604,7 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
 
        if (new_bind_flag == PIPE_BIND_LINEAR) {
                assert(!tex->htile_offset);
-               assert(!tex->cmask_size);
+               assert(!tex->cmask_buffer);
                assert(!tex->surface.fmask_size);
                assert(!tex->dcc_offset);
                assert(!tex->is_depth);
@@ -763,7 +763,7 @@ static boolean si_texture_get_handle(struct pipe_screen* screen,
                }
 
                if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
-                   (tex->cmask_size || tex->dcc_offset)) {
+                   (tex->cmask_buffer || tex->dcc_offset)) {
                        /* Eliminate fast clear (both CMASK and DCC) */
                        si_eliminate_fast_color_clear(sctx, tex);
                        /* eliminate_fast_color_clear flushes the context */
@@ -772,7 +772,7 @@ static boolean si_texture_get_handle(struct pipe_screen* screen,
                        /* Disable CMASK if flush_resource isn't going
                         * to be called.
                         */
-                       if (tex->cmask_size)
+                       if (tex->cmask_buffer)
                                si_texture_discard_cmask(sscreen, tex);
                }
 
@@ -986,7 +986,7 @@ void si_print_texture_info(struct si_screen *sscreen,
                                tex->surface.u.gfx9.fmask.epitch);
                }
 
-               if (tex->cmask_size) {
+               if (tex->cmask_buffer) {
                        u_log_printf(log, "  CMask: offset=%"PRIu64", size=%u, "
                                "alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
                                tex->cmask_offset,
@@ -1040,10 +1040,10 @@ void si_print_texture_info(struct si_screen *sscreen,
                        tex->surface.u.legacy.fmask.slice_tile_max,
                        tex->surface.u.legacy.fmask.tiling_index);
 
-       if (tex->cmask_size)
+       if (tex->cmask_buffer)
                u_log_printf(log, "  CMask: offset=%"PRIu64", size=%u, alignment=%u, "
                        "slice_tile_max=%u\n",
-                       tex->cmask_offset, tex->cmask_size, tex->surface.cmask_alignment,
+                       tex->cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment,
                        tex->surface.u.legacy.cmask_slice_tile_max);
 
        if (tex->htile_offset)
@@ -1185,13 +1185,12 @@ si_texture_create_object(struct pipe_screen *screen,
                        tex->size = tex->fmask_offset + tex->surface.fmask_size;
 
                        /* Allocate CMASK. */
-                       tex->cmask_size = tex->surface.cmask_size;
                        tex->cmask_offset = align64(tex->size, tex->surface.cmask_alignment);
-                       tex->size = tex->cmask_offset + tex->cmask_size;
+                       tex->size = tex->cmask_offset + tex->surface.cmask_size;
                        tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
                        tex->cmask_buffer = &tex->buffer;
 
-                       if (!tex->surface.fmask_size || !tex->cmask_size) {
+                       if (!tex->surface.fmask_size || !tex->surface.cmask_size) {
                                FREE(tex);
                                return NULL;
                        }
@@ -1231,10 +1230,10 @@ si_texture_create_object(struct pipe_screen *screen,
                        resource->gart_usage = buf->size;
        }
 
-       if (tex->cmask_size) {
+       if (tex->cmask_buffer) {
                /* Initialize the cmask to 0xCC (= compressed state). */
                si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b,
-                                        tex->cmask_offset, tex->cmask_size,
+                                        tex->cmask_offset, tex->surface.cmask_size,
                                         0xCCCCCCCC);
        }
        if (tex->htile_offset) {