cpuif: remove limitations on csr data_width

diff --git a/misoclib/gensoc/cpuif.py b/misoclib/gensoc/cpuif.py
index 82d5cdbcfc4b785717b8ecb14bb223d36470e095..2646711d8eea19428e471105d0132e4927cd6074 100644 (file)
--- a/misoclib/gensoc/cpuif.py
+++ b/misoclib/gensoc/cpuif.py
@@ -1,3 +1,4 @@
+from migen.fhdl.std import *
 from migen.bank.description import CSRStatus
 
 def get_cpu_mak(cpu_type):
@@ -28,19 +29,20 @@ def get_mem_header(regions, flash_boot_address):
        r += "#endif\n"
        return r
 
-def _get_rw_functions(reg_name, reg_base, size, read_only):
+def _get_rw_functions(reg_name, reg_base, nwords, busword, read_only):
        r = ""
 
        r += "#define CSR_"+reg_name.upper()+"_ADDR "+hex(reg_base)+"\n"
-       r += "#define CSR_"+reg_name.upper()+"_SIZE "+str(size)+"\n"
+       r += "#define CSR_"+reg_name.upper()+"_SIZE "+str(nwords)+"\n"
 
-       if size > 8:
+       size = nwords*busword
+       if size > 64:
                raise NotImplementedError("Register too large")
-       elif size > 4:
+       elif size > 32:
                ctype = "unsigned long long int"
-       elif size > 2:
+       elif size > 16:
                ctype = "unsigned int"
-       elif size > 1:
+       elif size > 8:
                ctype = "unsigned short int"
        else:
                ctype = "unsigned char"
@@ -48,21 +50,21 @@ def _get_rw_functions(reg_name, reg_base, size, read_only):
        r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
        if size > 1:
                r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
-               for byte in range(1, size):
-                       r += "\tr <<= 8;\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
+               for byte in range(1, nwords):
+                       r += "\tr <<= "+str(busword)+";\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
                r += "\treturn r;\n}\n"
        else:
                r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
 
        if not read_only:
                r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
-               for byte in range(size):
-                       shift = (size-byte-1)*8
+               for word in range(nwords):
+                       shift = (nwords-word-1)*busword
                        if shift:
                                value_shifted = "value >> "+str(shift)
                        else:
                                value_shifted = "value"
-                       r += "\tMMPTR("+hex(reg_base+4*byte)+") = "+value_shifted+";\n"
+                       r += "\tMMPTR("+hex(reg_base+4*word)+") = "+value_shifted+";\n"
                r += "}\n"
        return r
 
@@ -72,9 +74,10 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
                r += "\n/* "+name+" */\n"
                reg_base = csr_base + 0x800*mapaddr
                r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
+               busword = flen(rmap.bus.dat_w)
                for csr in csrs:
-                       nr = (csr.size + 7)//8
-                       r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, isinstance(csr, CSRStatus))
+                       nr = (csr.size + busword - 1)//busword
+                       r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, busword, isinstance(csr, CSRStatus))
                        reg_base += 4*nr
                try:
                        interrupt_nr = interrupt_map[name]
@@ -93,8 +96,9 @@ def get_csr_csv(csr_base, bank_array):
        r = ""
        for name, csrs, mapaddr, rmap in bank_array.banks:
                reg_base = csr_base + 0x800*mapaddr
+               busword = flen(rmap.bus.dat_w)
                for csr in csrs:
-                       nr = (csr.size + 7)//8
+                       nr = (csr.size + busword - 1)//busword
                        r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, reg_base, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
                        reg_base += 4*nr
        return r