+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386-intel.c (i386_intel_operand): Also handle DWORD
+ with 64-bit mode branches.
+ * testsuite/gas/i386/x86-64-jump.s: Extend Intel syntax branch
+ operand coverage.
+ * testsuite/gas/i386/x86-64-jump.d: Adjust expectations.
+
2019-12-04 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (output_insn): Don't consider Cpu* settings
&& current_templates->start->name[3] == 0)
|| current_templates->start->base_opcode == 0x62 /* bound */)
suffix = WORD_MNEM_SUFFIX;
- else if (flag_code == CODE_16BIT
+ else if (flag_code != CODE_32BIT
&& (current_templates->start->opcode_modifier.jump == JUMP
|| current_templates->start->opcode_modifier.jump
== JUMP_DWORD))
- suffix = LONG_DOUBLE_MNEM_SUFFIX;
+ suffix = flag_code == CODE_16BIT ? LONG_DOUBLE_MNEM_SUFFIX
+ : WORD_MNEM_SUFFIX;
else if (got_a_float == 1) /* "f..." */
suffix = SHORT_MNEM_SUFFIX;
else
[ ]*[a-f0-9]+: e3 00 jrcxz 0x69 68: R_X86_64_PC8 \$\+0x1
[ ]*[a-f0-9]+: 90 nop
[ ]*[a-f0-9]+: 66 ff 13 callw \*\(%rbx\)
+[ ]*[a-f0-9]+: 66 ff 1b lcallw \*\(%rbx\)
+[ ]*[a-f0-9]+: ff 1b lcall \*\(%rbx\)
+[ ]*[a-f0-9]+: ff 13 callq \*\(%rbx\)
+[ ]*[a-f0-9]+: ff 13 callq \*\(%rbx\)
[ ]*[a-f0-9]+: ff 1b lcall \*\(%rbx\)
[ ]*[a-f0-9]+: 66 ff 23 jmpw \*\(%rbx\)
+[ ]*[a-f0-9]+: 66 ff 2b ljmpw \*\(%rbx\)
+[ ]*[a-f0-9]+: ff 2b ljmp \*\(%rbx\)
+[ ]*[a-f0-9]+: ff 23 jmpq \*\(%rbx\)
+[ ]*[a-f0-9]+: ff 23 jmpq \*\(%rbx\)
[ ]*[a-f0-9]+: ff 2b ljmp \*\(%rbx\)
-[ ]*[a-f0-9]+: eb 00 jmp 0x76
+[ ]*[a-f0-9]+: eb 00 jmp 0x[0-9a-f]*
[ ]*[a-f0-9]+: 90 nop
-[ ]*[a-f0-9]+: 67 e3 00 jecxz 0x7a
+[ ]*[a-f0-9]+: 67 e3 00 jecxz 0x[0-9a-f]*
[ ]*[a-f0-9]+: 90 nop
-[ ]*[a-f0-9]+: e3 00 jrcxz 0x7d
+[ ]*[a-f0-9]+: e3 00 jrcxz 0x[0-9a-f]*
[ ]*[a-f0-9]+: 90 nop
-[ ]*[a-f0-9]+: eb 00 jmp 0x80
+[ ]*[a-f0-9]+: eb 00 jmp 0x[0-9a-f]*
#pass