Merge branch 'master' into trigger

Conflicts:
	riscv/encoding.h
	riscv/processor.cc

diff --cc riscv/processor.cc
index e1f132e8b66ab11ba38c48f273bd1a50133bd77c,78fb5f11ec20ab87205b41360a95907674e10265..6d0b98356d6b11fb410c3db8a141ce29ac435b4b
--- 1/riscv/processor.cc
--- 2/riscv/processor.cc
+++ b/riscv/processor.cc
@@@ -521,38 -494,10 +534,39 @@@ reg_t processor_t::get_csr(int which
      case CSR_MTVEC: return state.mtvec;
      case CSR_MEDELEG: return state.medeleg;
      case CSR_MIDELEG: return state.mideleg;
 -    case CSR_TSELECT: return 0;
 -    case CSR_TDATA1: return 0;
 -    case CSR_TDATA2: return 0;
 +    case CSR_TSELECT: return state.tselect;
 +    case CSR_TDATA1:
 +      if (state.tselect < state.num_triggers) {
 +        reg_t v = 0;
 +        mcontrol_t *mc = &state.mcontrol[state.tselect];
 +        v = set_field(v, MCONTROL_TYPE(xlen), mc->type);
 +        v = set_field(v, MCONTROL_DMODE(xlen), mc->dmode);
 +        v = set_field(v, MCONTROL_MASKMAX(xlen), mc->maskmax);
 +        v = set_field(v, MCONTROL_SELECT, mc->select);
 +        v = set_field(v, MCONTROL_TIMING, mc->timing);
 +        v = set_field(v, MCONTROL_ACTION, mc->action);
 +        v = set_field(v, MCONTROL_CHAIN, mc->chain);
 +        v = set_field(v, MCONTROL_MATCH, mc->match);
 +        v = set_field(v, MCONTROL_M, mc->m);
 +        v = set_field(v, MCONTROL_H, mc->h);
 +        v = set_field(v, MCONTROL_S, mc->s);
 +        v = set_field(v, MCONTROL_U, mc->u);
 +        v = set_field(v, MCONTROL_EXECUTE, mc->execute);
 +        v = set_field(v, MCONTROL_STORE, mc->store);
 +        v = set_field(v, MCONTROL_LOAD, mc->load);
 +        return v;
 +      } else {
 +        return 0;
 +      }
 +      break;
 +    case CSR_TDATA2:
 +      if (state.tselect < state.num_triggers) {
 +        return state.tdata2[state.tselect];
 +      } else {
 +        return 0;
 +      }
 +      break;
+     case CSR_TDATA3: return 0;
      case CSR_DCSR:
        {
          uint32_t v = 0;

diff --cc riscv/processor.h
Simple merge