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add reg table
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 14 Apr 2018 00:00:19 +0000
(
01:00
+0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 14 Apr 2018 00:00:19 +0000
(
01:00
+0100)
alt_rvp.mdwn
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diff --git
a/alt_rvp.mdwn
b/alt_rvp.mdwn
index 2f4b6063c79978d03e0fd5c64ee513275b251d16..c920137c4ac1fa25febda07190adf22d57721a32 100644
(file)
--- a/
alt_rvp.mdwn
+++ b/
alt_rvp.mdwn
@@
-1,5
+1,13
@@
# Lanes
+Register table
+
+| reg num | Lane 0 | Lane 1 | Lane 2 | Lane 3 |
+| ------- | ------ | ------ | ------ | ------ |
+| r0 | (31.0) | (31.0) | (31.0) | (31.0) |
+| r1 | (31.0) | (31.0) | (31.0) | (31.0) |
+| r2 | (31.0) | (31.0) | (31.0) | (31.0) |
+
Example parallel add:
/* XLEN and N are "baked-in" to the hardware */