bus/csr: allow specifying existing interface

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 0bce395dec37f1df22f7cfa9ff6e7deed37cfbc3..df2543482af08916fb5ab0b66a1ecd9ec0087190 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -17,9 +17,9 @@ class Interconnect(SimpleInterconnect):
        pass
 
 class Initiator(PureSimulable):
-       def __init__(self, generator):
+       def __init__(self, generator, bus=Interface()):
                self.generator = generator
-               self.bus = Interface()
+               self.bus = bus
                self.transaction = None
                self.done = False