vk/cmd_buffer: Move the re-emission of STATE_BASE_ADDRESS to the flushing code

This used to happen magically in cmd_buffer_new_surface_state_bo.  However,
according to Ken, STATE_BASE_ADDRESS is very gen-specific so we really
shouldn't have it in the generic data-structure code.

diff --git a/src/vulkan/anv_cmd_buffer.c b/src/vulkan/anv_cmd_buffer.c
index f7d6990157b6bfaa580882bd18a163841d14cf46..34916386b6a34eb75e01f0972c1afa8f84b7bbd6 100644 (file)
--- a/src/vulkan/anv_cmd_buffer.c
+++ b/src/vulkan/anv_cmd_buffer.c
@@ -345,51 +345,6 @@ anv_cmd_buffer_new_surface_state_bo(struct anv_cmd_buffer *cmd_buffer)
    new_bbo->prev_batch_bo = old_bbo;
    cmd_buffer->surface_batch_bo = new_bbo;
 
-   /* Re-emit state base addresses so we get the new surface state base
-    * address before we start emitting binding tables etc.
-    */
-   anv_cmd_buffer_emit_state_base_address(cmd_buffer);
-
-   /* After re-setting the surface state base address, we have to do some
-    * cache flusing so that the sampler engine will pick up the new
-    * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
-    * Shared Function > 3D Sampler > State > State Caching (page 96):
-    *
-    *    Coherency with system memory in the state cache, like the texture
-    *    cache is handled partially by software. It is expected that the
-    *    command stream or shader will issue Cache Flush operation or
-    *    Cache_Flush sampler message to ensure that the L1 cache remains
-    *    coherent with system memory.
-    *
-    *    [...]
-    *
-    *    Whenever the value of the Dynamic_State_Base_Addr,
-    *    Surface_State_Base_Addr are altered, the L1 state cache must be
-    *    invalidated to ensure the new surface or sampler state is fetched
-    *    from system memory.
-    *
-    * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
-    * which, according the PIPE_CONTROL instruction documentation in the
-    * Broadwell PRM:
-    *
-    *    Setting this bit is independent of any other bit in this packet.
-    *    This bit controls the invalidation of the L1 and L2 state caches
-    *    at the top of the pipe i.e. at the parsing time.
-    *
-    * Unfortunately, experimentation seems to indicate that state cache
-    * invalidation through a PIPE_CONTROL does nothing whatsoever in
-    * regards to surface state and binding tables.  In stead, it seems that
-    * invalidating the texture cache is what is actually needed.
-    *
-    * XXX:  As far as we have been able to determine through
-    * experimentation, shows that flush the texture cache appears to be
-    * sufficient.  The theory here is that all of the sampling/rendering
-    * units cache the binding table in the texture cache.  However, we have
-    * yet to be able to actually confirm this.
-    */
-   anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
-                  .TextureCacheInvalidationEnable = true);
-
    return VK_SUCCESS;
 }
 

diff --git a/src/vulkan/anv_cmd_emit.c b/src/vulkan/anv_cmd_emit.c
index 8654c4a0ac734184ad1865ea628a8c28a91ed842..61d58be33a64656cec7cca0960a8de6407574a5b 100644 (file)
--- a/src/vulkan/anv_cmd_emit.c
+++ b/src/vulkan/anv_cmd_emit.c
@@ -504,6 +504,51 @@ flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
       result = anv_cmd_buffer_new_surface_state_bo(cmd_buffer);
       assert(result == VK_SUCCESS);
 
+      /* Re-emit state base addresses so we get the new surface state base
+       * address before we start emitting binding tables etc.
+       */
+      anv_cmd_buffer_emit_state_base_address(cmd_buffer);
+
+      /* After re-setting the surface state base address, we have to do
+       * some cache flusing so that the sampler engine will pick up the new
+       * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
+       * Shared Function > 3D Sampler > State > State Caching (page 96):
+       *
+       *    Coherency with system memory in the state cache, like the
+       *    texture cache is handled partially by software. It is expected
+       *    that the command stream or shader will issue Cache Flush
+       *    operation or Cache_Flush sampler message to ensure that the L1
+       *    cache remains coherent with system memory.
+       *
+       *    [...]
+       *
+       *    Whenever the value of the Dynamic_State_Base_Addr,
+       *    Surface_State_Base_Addr are altered, the L1 state cache must be
+       *    invalidated to ensure the new surface or sampler state is
+       *    fetched from system memory.
+       *
+       * The PIPE_CONTROL command has a "State Cache Invalidation Enable"
+       * bit which, according the PIPE_CONTROL instruction documentation in
+       * the Broadwell PRM:
+       *
+       *    Setting this bit is independent of any other bit in this
+       *    packet.  This bit controls the invalidation of the L1 and L2
+       *    state caches at the top of the pipe i.e. at the parsing time.
+       *
+       * Unfortunately, experimentation seems to indicate that state cache
+       * invalidation through a PIPE_CONTROL does nothing whatsoever in
+       * regards to surface state and binding tables.  In stead, it seems
+       * that invalidating the texture cache is what is actually needed.
+       *
+       * XXX:  As far as we have been able to determine through
+       * experimentation, shows that flush the texture cache appears to be
+       * sufficient.  The theory here is that all of the sampling/rendering
+       * units cache the binding table in the texture cache.  However, we
+       * have yet to be able to actually confirm this.
+       */
+      anv_batch_emit(&cmd_buffer->batch, GEN8_PIPE_CONTROL,
+                     .TextureCacheInvalidationEnable = true);
+
       /* Re-emit all active binding tables */
       for_each_bit(s, cmd_buffer->state.pipeline->active_stages) {
          result = flush_descriptor_set(cmd_buffer, s);