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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 58537473112441783e920764c3a6122871e23397..d04d66de7bbe57c04efdf0d31ba88f613fe1b8f7 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -548,13 +548,11 @@ is performed, and if it fails it is considered to have been
 *as if* the destination predicate bit was zero.
 Arithmetic and Logical Pred-result is covered in [[sv/normal]]
 
-## pred-result mode on CR ops
+Ped-result mode may not be applied on CR ops.
 
-CR operations (mtcr, crand, cror) may be Vectorised,
-predicated, and also pred-result mode applied to it.  
-Vectorisation applies to 4-bit CR Fields which are treated as
-elements, not the individual bits of the 32-bit CR.
-CR ops and how to identify them is described in [[sv/cr_ops]]
+Although CR operations (mtcr, crand, cror) may be Vectorised,
+predicated, pred-result mode applies to operations that have
+an Rc=1 mode, or make sense to add an RC1 option.
 
 # CR Operations