abc9: add some log_{push,pop}() as per @nakengelhardt

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 6a296bfe7fa4b9d76e0257d06540f31785da6e59..f4a89efffa1d85debefd110bee7691cc3761d3f6 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -235,8 +235,11 @@ struct Abc9Pass : public ScriptPass
                extra_args(args, argidx, design);
 
                log_header(design, "Executing ABC9 pass.\n");
+               log_push();
 
                run_script(design, run_from, run_to);
+
+               log_pop();
        }
 
        void script() YS_OVERRIDE
@@ -276,6 +279,7 @@ struct Abc9Pass : public ScriptPass
                                        }
                                        log_assert(!mod->attributes.count(ID(abc9_box_id)));
 
+                                       log_push();
                                        active_design->selection().select(mod);
 
                                        if (!active_design->selected_whole_module(mod))
@@ -310,6 +314,7 @@ struct Abc9Pass : public ScriptPass
                                        }
 
                                        active_design->selection().selected_modules.clear();
+                                       log_pop();
                                }
 
                                active_design->selection_stack.pop_back();

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 034731b87c1b58f482c95b2a2b856811df6c2088..cf2ac16c97736c6a439f810344d5bec581ef6f8c 100644 (file)
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -397,18 +397,21 @@ struct AlumaccWorker
                {
                        log("  creating $alu model for %s (%s):", log_id(cell), log_id(cell->type));
 
-                       bool cmp_less = cell->type.in(ID($lt), ID($le));
-                       bool cmp_equal = cell->type.in(ID($le), ID($ge));
+                       bool cmp_less = false; //cell->type.in(ID($lt), ID($le));
+                       bool cmp_equal = false; //cell->type.in(ID($le), ID($ge));
                        bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
 
                        RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
                        RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
                        RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
 
-                       if (B < A && GetSize(B)) {
-                               cmp_less = !cmp_less;
+                       if (cell->type.in(ID($lt), ID($ge)))
                                std::swap(A, B);
-                       }
+
+                       //if (B < A && GetSize(B)) {
+                       //      cmp_less = !cmp_less;
+                       //      std::swap(A, B);
+                       //}
 
                        alunode_t *n = nullptr;
 
@@ -432,6 +435,12 @@ struct AlumaccWorker
                                log(" merged with %s.\n", log_id(n->cells.front()));
                        }
 
+                       if (cell->type.in(ID($le), ID($ge))) {
+                               SigSpec YY = module->addWire(NEW_ID, GetSize(Y));
+                               module->addNot(NEW_ID, YY, Y);
+                               Y = YY;
+                       }
+
                        n->cells.push_back(cell);
                        n->cmp.push_back(std::make_tuple(cmp_less, !cmp_less, cmp_equal, false, Y));
                }