i386: Require OPTION_MASK_ISA_SSE2 for __builtin_ia32_movq128 [PR94603]

	PR target/94603
	* config/i386/i386-builtin.def (__builtin_ia32_movq128):
	Require OPTION_MASK_ISA_SSE2.

testsuite/ChangeLog:

	PR target/94603
	* gcc.target/i386/pr94603.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6148a8276c9a9677c167aedde5df0562fc8de161..ae08fbec2f715a1bd33792bc5e80b9f6a58b72a5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-15  Uroš Bizjak  <ubizjak@gmail.com>
+
+       PR target/94603
+       * config/i386/i386-builtin.def (__builtin_ia32_movq128):
+       Require OPTION_MASK_ISA_SSE2.
+
 2020-04-15  Gustavo Romero  <gromero@linux.ibm.com>
 
        PR bootstrap/89494

diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index bae561bc7f4fc2e9ab3c728c53af60b6e8282cce..4d5863ce0aae42849e6cac6a1efded1260895b46 100644 (file)
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -811,7 +811,7 @@ BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw",
 
 BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE)
 
-BDESC (OPTION_MASK_ISA_SSE, 0, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI)
+BDESC (OPTION_MASK_ISA_SSE2, 0, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI)
 
 /* SSE2 MMX */
 BDESC (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI)

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e4fc22197e644700ebe8b448add5c7f74eb4dce0..8181e9df8467c4650a21379d9993bc8cbcadbafd 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-15  Uroš Bizjak  <ubizjak@gmail.com>
+
+       PR target/94603
+       * gcc.target/i386/pr94603.c: New test.
+
 2020-04-15  Andre Vieira <andre.simoesdiasvieira@arm.com>
             Srinath Parvathaneni <srinath.parvathaneni@arm.com>
 

diff --git a/gcc/testsuite/gcc.target/i386/pr94603.c b/gcc/testsuite/gcc.target/i386/pr94603.c
new file mode 100644 (file)
index 0000000..34a1e06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr94603.c
@@ -0,0 +1,11 @@
+/* PR target/94603 */
+/* { dg-do compile } */
+/* { dg-options "-Wno-implicit-function-declaration -msse -mno-sse2" } */
+
+typedef long long __attribute__ ((__vector_size__ (16))) V;
+
+V
+foo (V v)
+{
+  return __builtin_ia32_movq128 (v);  /* { dg-error "" } */
+}