*/
if (!rscreen->info.has_dedicated_vram &&
(rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
- res->domains == RADEON_DOMAIN_VRAM)
+ res->domains == RADEON_DOMAIN_VRAM) {
res->domains = RADEON_DOMAIN_VRAM_GTT;
+ res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
+ }
if (rscreen->debug_flags & DBG_NO_WC)
res->flags &= ~RADEON_FLAG_GTT_WC;
}
enum radeon_heap {
+ RADEON_HEAP_VRAM_NO_CPU_ACCESS,
RADEON_HEAP_VRAM,
RADEON_HEAP_VRAM_GTT, /* combined heaps */
RADEON_HEAP_GTT_WC,
static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
{
switch (heap) {
+ case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
case RADEON_HEAP_VRAM:
return RADEON_DOMAIN_VRAM;
case RADEON_HEAP_VRAM_GTT:
static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
{
switch (heap) {
+ case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
+ return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
case RADEON_HEAP_VRAM:
case RADEON_HEAP_VRAM_GTT:
case RADEON_HEAP_GTT_WC:
{
/* VRAM implies WC (write combining) */
assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
+ /* NO_CPU_ACCESS implies VRAM only. */
+ assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
- /* Unsupported flags: NO_CPU_ACCESS, NO_SUBALLOC, SPARSE. */
- if (flags & ~RADEON_FLAG_GTT_WC)
+ /* Unsupported flags: NO_SUBALLOC, SPARSE. */
+ if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS))
return -1;
switch (domain) {
case RADEON_DOMAIN_VRAM:
- return RADEON_HEAP_VRAM;
+ if (flags & RADEON_FLAG_NO_CPU_ACCESS)
+ return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
+ else
+ return RADEON_HEAP_VRAM;
case RADEON_DOMAIN_VRAM_GTT:
return RADEON_HEAP_VRAM_GTT;
case RADEON_DOMAIN_GTT:
/* VRAM implies WC. This is not optional. */
assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
+ /* NO_CPU_ACCESS is valid with VRAM only. */
+ assert(domain == RADEON_DOMAIN_VRAM || !(flags & RADEON_FLAG_NO_CPU_ACCESS));
+
/* Sub-allocate small buffers from slabs. */
if (!(flags & (RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_SPARSE)) &&
size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) &&
/* VRAM implies WC. This is not optional. */
if (domain & RADEON_DOMAIN_VRAM)
flags |= RADEON_FLAG_GTT_WC;
+ /* NO_CPU_ACCESS is valid with VRAM only. */
+ if (domain != RADEON_DOMAIN_VRAM)
+ flags &= ~RADEON_FLAG_NO_CPU_ACCESS;
/* Sub-allocate small buffers from slabs. */
if (!(flags & RADEON_FLAG_NO_SUBALLOC) &&