{% trans path=pathto('copyright'), copyright=copyright|e %}© <a href="{{ path }}">Copyright</a> {{ copyright }}.{% endtrans %}
{%- else %}
<!-- {% trans copyright=copyright|e %}© Copyright {{ copyright }}.{% endtrans %} -->
- © Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">EnjoyDigital and M-Labs Contributors</a>.
+ © Copyright {{ copyright }} <a href="{{ pathto("docs\contributing\AUTHORS") }}">HKU</a>.
<!-- update theme to remove the translation stuff here - it was breaking due to link to AUTHORS file. This is a cludge to allow specific link to my authors file -->
{%- endif %}
{%- endif %}
- send us feedback and suggestions for improvements
- send us bug reports when something goes wrong
- send us the modifications and improvements you have done to LiteSATA.
-The use of "git format-patch" is recommended. If your submission is large and
-complex and/or you are not sure how to proceed, feel free to discuss it with us.
+ The use of "git format-patch" is recommended. If your submission is large and
+ complex and/or you are not sure how to proceed, feel free to discuss it with us.
Now that you know why LiteSATA is the :ref:`core for you <about>`, it's time to *get started*.
-This section explains the procedure for :ref:`downloading and installing the tools`.
+This section explains the procedure for downloading and installing the tools.
.. toctree::
:maxdepth: 1
Frontend:
- Configurable crossbar (simply declare your crossbar and use core.crossbar.get_port() to add a new port!)
- Ports arbitration transparent to the user
- - Synthetizable BIST
+ - Synthesizable BIST
- Striping module to segment data on multiple HDDs and increase write/read speed and capacity. (RAID0 equivalent)
- Mirroring module for data redundancy and increase read speeds. (RAID1 equivalent)
Contact
=======
E-mail: florent [AT] enjoy-digital.fr
-
-
proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
+
- tell us that you are using LiteSATA
- cite LiteSATA in publications related to research it has helped
- send us feedback and suggestions for improvements
::
- Unless otherwise noted, LiteSATA is copyright (C) 2015 HKU.
+ Unless otherwise noted, LiteSATA is copyright (C) 2014-2015 HKU.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
=========
0.9.0:
- First release supporting Xilinx Kintex7.
-
Talks and Publications
======================
-- Migen / MiSoC documentation:
- - `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
- - `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
+ - Migen / MiSoC documentation:
+ - `User guide <http://m-labs.hk/migen.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
+ - `Tutorial: An introduction to Migen <http://m-labs.hk/migen-tutorial.pdf>`_ (`m-labs <https://github.com/m-labs>`_)
-- Migen / MiSoC presentations:
- - `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- - `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
- - `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)
+ - Migen / MiSoC presentations:
+ - `Lecture slides <http://m-labs.hk/migen-slides.pdf>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
+ - `EHSM 2012 presentation <https://www.youtube.com/watch?v=yxKMsAi_WEA>`_ (`sbourdeauducq <https://github.com/sbourdeauducq>`_)
+ - `ORCONF2014 <https://www.youtube.com/watch?v=AfEPbw4nREo>`_ (`fallen <https://github.com/fallen>`_)
.. _phy-index:
-========================
+===
PHY
-========================
+===
.. note::
Please contribute to this document, or support us financially to write it.
\ No newline at end of file
.. _simulation-index:
-========================
+==========
Simulation
-========================
+==========
.. note::
Please contribute to this document, or support us financially to write it.
Simulations are available in ./test:
+
- :code:`crc_tb`
- :code:`scrambler_tb`
- :code:`phy_datapath_tb`
Models for all the layers of SATA and a simplified HDD model are provided.
To run a simulation, go to ./test and run:
- - :code:`make <simulation_name>`
\ No newline at end of file
+
+ - :code:`make <simulation_name>`
========================
.. note::
- This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
+ This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
Serial Advanced Technology Attachment (SATA) is a serial link replacement of
Parallel ATA (PATA), both standards for communication with mass storage devices.
SATA layers.
-SATA’s architecture consists of four layers, Application, Transport, Link, and Physical.
+SATA's architecture consists of four layers, Application, Transport, Link, and Physical.
The Application layer is responsible for overall ATA commands and of controlling SATA
register accesses. The transport layer places control information and data to be transferred between
the host and corresponding SATA device in a data packets. One such packet is called a frame
==============
This section describes the physical interface towards the actual SATA link.
The features of the phy can be summarized to:
+
- Transmit/Receive a 1.5 Gbps, 3.0 or 6.0 Gbps differential signal
- Speed negotiation
- OOB detection and transmission
==========
This section describes the SATA link layer.
The link layer’s major tasks are:
+
- Flow control
- Encapsulate FISes received from transport layer
- CRC generation and CRC check
===============
The main task for the SATA transport layer is to handle FISes and a brief description
of the layer’s features follows:
+
- Flow control
- Error control
- Error reporting
The flow control in this case is only to report to the link layer that the data buffers
are close to over- or underflow. Errors detected are supposed to be reported to
the application layer and the detectable errors are:
+
- Errors from lower layers like 8b/10b disparity error or CRC errors.
- SATA state or protocol errors caused by standard violation.
- Frame errors like malformed header.
the costs of a large buffer can be spared.
Command Layer
-=================
+=============
The command layer tells the transport layer what kind of FISes to send and receive
for each specific command and in which order those FISes are expexted to be delivered.
.. note::
- This chapter is a lightly modified version of the excellent SATA summerization found in Chapter 2 of Erik Landström's Thesis_.
+ This chapter is a lightly modified version of the excellent SATA summary found in Chapter 2 of Erik Landström's Thesis_.
.. _Thesis: http://www.diva-portal.org/smash/get/diva2:207798/FULLTEXT01.pdf
.. _test-index:
-========================
+====
Test
-========================
+====
.. note::
Please contribute to this document, or support us financially to write it.
A synthetizable BIST is provided and can be controlled with ./test/bist.py.
By using LiteScope and the provided ./test/test_link.py example you are able to
-visualize the internal logic of the design and even inject the captured data in
-the HDD model!
\ No newline at end of file
+visualize the internal logic of the design and even inject the captured data into
+the HDD model!
<img alt="./_static/LiteSATA_logo_full.png" src="_static/LiteSATA_logo_full.png">
-<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2/3 core</b>.</h3>
+<h3>LiteSATA provides a <b>small footprint and configurable FPGA SATA gen1/2 core</b>.</h3>
<div class="container" style="width:100%;margin-bottom:10px;">
<div class="one-third-container" style="width:32%; display:inline-block;">
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Small footprint</div>
- <div class="signpost-body" style=""><p>Thanks to simple and efficient Migen's building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
+ <div class="signpost-body" style=""><p>Thanks to simple and efficient Migen building blocks and the KISS principe used to develop this core, LiteSATA footprint is really small!</p></div>
</div>
</div>
<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px;margin-right:5px;">
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Configurable</div>
- <div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen as a Python meta-language. The core is then easily configurable to fit
- user's needs! (Number of crossbar ports, included BIST and so on...)</p></div>
+ <div class="signpost-body" style=""><p>LiteSATA generates HDL using Migen, a Python-based logic design system. The core is easily configurable to fit
+ user's needs! (number of crossbar ports, RAID configuration, included BIST and so on...)</p></div>
</div>
</div>
<div class="one-third-container" style="width:32%; display:inline-block; font-style:bold;">
<div class="signpost" style="display:inline-block; vertical-align:text-top; margin-left:5px; margin-right:5px;">
<div class="signpost-heading" style="font-size:2em; font-style:bold; margin-bottom:10px;">Portable</div>
- <div class="signpost-body" style=""><p>Porting the core to another vendor or family only require adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
+ <div class="signpost-body" style=""><p>Porting the core to another vendor or family only requires adapting or adding a new PHY. All others building blocks of the core are generic.</p></div>
</div>
</div>
</div>
-
docs/frontend/index
docs/simulation/index
docs/test/index
- docs/site/about
-
projects / litex.git / commitdiff