(no commit message)

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 14ce3e2083d825d8dd296a18b2b6410a34847c10..1ee91bdf1b7f22996d6a55bc4178c6090accc285 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -2,6 +2,8 @@
 
 # New instructions for CR/INT predication
 
+**DRAFT STATUS**
+
 See:
 
 * main bugreport for crweirds
@@ -64,7 +66,7 @@ the CR Register, not to individual bits within the CR register.
 
 # Instruction form and pseudocode
 
-Instruction format:
+**DRAFT** Instruction format (use of MAJOR 19 not approved):
 
 |0-5|6-10 |11|12-15|16-18|19-20|21-25  |26-30  |31|name      |
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |